Principal Digital Designer, HIG HBM - Richardson, TX, United States
Originally posted 1 April 2026 by the employer.
About the role
As a Principal HBM RTL Designer, you will serve as a technical leader driving the front-end digital design of High Bandwidth Memory (HBM) products. You will own complex design blocks end-to-end from architectural definition through production implementation for HBM subsystems.
What you'll do
- Define, architect, and lead the development of advanced RTL blocks for HBM subsystems, aligning with product requirements and architectural goals. - Own end-to-end front-end design, including micro-architecture, RTL development, simulation strategy, and design quality. - Drive technical decisions across circuit development, synthesis, constraints, and physical-design integration to achieve timing, power, and area compliance. - Champion design methodologies, develop reusable frameworks, and improve RTL design flows, validation strategies, and sign-off processes. - Collaborate with physical design, verification, architecture, and product engineering to integrate subsystems and deliver silicon. - Lead root-cause analysis and corrective actions for complex design issues to maintain design robustness.
What you'll need
- Bachelor's degree with 9+ years of experience, or Master's degree with 7+ years of experience in digital development and RTL development. - Expert-level knowledge of front-end digital design, RTL coding, micro-architecture, and system integration. - Deep understanding of timing closure, power optimization, area trade-offs, and system-level complexity management. - Strong experience with synthesis, STA, constraints, LEC, Lint, CDC, and front-end sign-off methodologies. - Proven ability to lead technical teams, mentor engineers, and influence build direction across large programs.
Nice to have
- Experience with UPF, power-intent development, power analysis, DFT/scan insertion, ATPG, and timing model generation. - Proficiency in Python, Perl, or scripting to automate and improve design flows. - Familiarity with place-and-route tools and back-end requirements for RTL-to-GDS integration. - Proven history delivering high-complexity systems in memory, high-speed I/O, or compute-intensive ASIC builds. - Ability to define architectural trade-offs, influence product direction, and guide teams toward scalable and maintainable build solutions.
Skills: RTL development, HBM subsystems, micro-architecture, timing closure, power optimization
This role has been open 222 days — well above the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
309
|
Median days open
71 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (309 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 309 |
| Median days open | 91 d | 71 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: RTL development, HBM subsystems, micro-architecture, timing closure, power optimization
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 91 d
- Synopsys · 30 open roles · median 67 d
- Qualcomm · 19 open roles · median 88 d
- Broadcom · 17 open roles · median 68 d
- SanDisk · 17 open roles · median 54 d
- NVIDIA · 7 open roles · median 34 d
How we counted: 309 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.