Principal Digital Design Engineer - San Jose, California, United States
$185,000 CAD yearly
Originally posted 14 September 2026 by the employer — open 0 days.
About the role
This role involves architecting and implementing digital designs for high-performance connectivity solutions, owning complex blocks from micro-architecture through silicon bring-up.
What you'll do
- Develop and implement complex digital blocks and subsystems, defining micro-architecture and driving digital design.
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug issues.
- Lead efforts for timing closure and implement Design-for-Test (DFT) features.
- Work closely with post-silicon teams for silicon bring-up and debug.
- Mentor junior engineers in technical skills.
- Contribute to the development and improvement of silicon development processes.
What you'll need
- Bachelor’s degree in electrical engineering or equivalent.
- 8+ years of experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
- Architecture definition and micro-architecture development expertise.
- RTL coding, functional simulation, and synthesis experience.
- Timing closure and gate-level simulation (GLS) experience.
- Design for test (DFT) implementation.
- Production experience with advanced CMOS nodes (≤7nm).
- Deep expertise in at least one high-speed protocol: PCIe, Ethernet, InfiniBand, DDR, or similar.
- Third-party IP integration and verification experience.
- Proficiency with Cadence and/or Synopsys digital design flows.
- Familiarity with UVM-based verification methodologies.
- Silicon bring-up, debug, and failure analysis expertise.
Nice to have
- Track record of delivering multiple high-performance designs to production in data-center environments.
- Hands-on collaboration with embedded firmware teams.
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.).
- Contributions to design methodology, CAD automation, or design infrastructure.
This role has been open 0 days — well below the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
946
|
Median days open
64 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (946 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 946 |
| Open roles in the wider Digital Design & Verification family | 48 | 3083 · 115 employers |
| Median days open | 40 d | 64 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Who's hiring in this category
- Qualcomm · 137 open roles · median 54 d
- AMD · 58 open roles · median 68 d
- NXP Semiconductors · 51 open roles · median 67 d
- Synopsys · 50 open roles · median 30 d
- NVIDIA · 48 open roles · median 49 d
- Marvell Technology · 41 open roles · median 120 d
How we counted: 946 open Digital/RTL Design (RTL Design) roles from 100 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.