Principal Digital Design Engineer - Chandler (Office)
Originally posted 18 September 2026 by the employer — open 0 days.
Design and implement digital architectures for Power Management ICs (PMICs) in automotive and industrial applications.
About the role
You will drive product execution from concept through RTL development, integration, silicon validation, qualification, and production release.
What you'll do
- Review product requirements, IP architecture specifications, programming models, microarchitecture, interfaces, and implementation plans.
- Define and implement digital architectures for mixed-signal PMICs.
- Lead digital design activities from architecture definition through RTL development, integration, synthesis, timing closure, low-power implementation, silicon bring-up, and production release.
- Design and develop digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault management functions for PMIC and power conversion products.
- Develop and review RTL, microarchitecture, and design specifications using Verilog/SystemVerilog and industry-standard design and quality checking tools.
- Drive verification strategy and execution, including test planning, simulation, formal verification, coverage analysis, and regression management.
What you'll need
- M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 12 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.
- Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low-power design techniques.
- Expertise in RTL design using Verilog/SystemVerilog for complex digital and mixed-signal ICs.
- Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.
- Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage-driven verification.
- Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.
This role has been open 0 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
941
|
Median days open
60 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (941 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 941 |
| Open roles in the wider Digital Design & Verification family | 144 | 3012 · 114 employers |
| Median days open | 66 d | 60 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 52 d
- AMD · 63 open roles · median 60 d
- Synopsys · 58 open roles · median 29 d
- NXP Semiconductors (this employer) · 53 open roles · median 66 d
- NVIDIA · 47 open roles · median 43 d
- Analog Devices · 39 open roles · median 72 d
How we counted: 941 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.