Principal Design Verification Engineer- SerDes/PHY IP - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 31 August 2026 by the employer.
This role owns functional verification of high-speed SerDes/PHY IP.
About the role
This role involves owning the functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success for SerDes/PHY IP powering rack-scale AI infrastructure.
What you'll do
- Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
- Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks.
- Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.
- Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
- Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios.
- Lead coverage analysis and closure, debug failures with designers, and drive regressions.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up.
- Expert-level proficiency in SystemVerilog and UVM.
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM).
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
- Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows.
- Scripting proficiency in Python or Perl for verification automation and regression management.
- Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results.
Skills: functional verification, SerDes/PHY IP, UVM-based verification environments, SystemVerilog, coverage closure
This role has been open 28 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1169 |
| Open roles in the wider Digital Design & Verification family | 57 | 3113 · 115 employers |
| Median days open | 44 d | 63 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: functional verification, SerDes/PHY IP, UVM-based verification environments, SystemVerilog, coverage closure
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.