Principal Design Verification Engineer - Plano, United States
Originally posted 29 September 2026 by the employer.
About the role
This role will provide technical leadership for verification of semiconductor memory interface products, including data buffer silicon. This is an opportunity to take significant technical ownership while contributing to DDR6 technology.
What you'll do
- Lead verification strategy and execution for complex semiconductor designs at the block and system level.
- Define verification methodologies, test plans, coverage strategies, and verification environments.
- Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
- Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
- Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff.
- Provide technical guidance and mentorship to verification engineers.
What you'll need
- Extensive experience in semiconductor design verification, with demonstrated technical ownership of complex verification efforts.
- Expert-level proficiency with SystemVerilog.
- Significant hands-on experience with UVM (Universal Verification Methodology), including development and optimization of UVM-based verification environments.
- Experience defining verification strategies and developing verification plans from design and product specifications.
- Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure.
- Ability to provide technical leadership and mentoring within a verification team.
Nice to have
- Experience with DDR, memory interfaces, memory controllers, data buffers, or related semiconductor technologies.
- Experience with DDR4 and/or DDR5.
- Verification experience with complex high-speed interfaces, protocols, or mixed-signal semiconductor products.
- Experience leading verification efforts through coverage closure and signoff.
Skills: semiconductor verification, SystemVerilog, UVM, DDR, functional coverage
This role has been open 11 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1189
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1189 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1189 |
| Open roles in the wider Digital Design & Verification family | 84 | 3166 · 114 employers |
| Median days open | 12 d | 64 d (−52 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: semiconductor verification, SystemVerilog, UVM, DDR, functional coverage
Who's hiring in this category
- Qualcomm · 106 open roles · median 43 d
- AMD · 103 open roles · median 50 d
- NVIDIA · 74 open roles · median 64 d
- Synopsys · 61 open roles · median 26 d
- SiFive · 54 open roles · median 67 d
- Cadence Design Systems · 51 open roles · median 109 d
How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.