Principal Design Verification Engineer
Technical ownership and verification leadership for memory interface products and DDR6 technology.
Originally posted 10 November 2026 by the employer.
About the role
The Principal Design Verification Engineer provides technical leadership for the verification of semiconductor memory interface products, including data buffer silicon. This role drives verification strategy and execution for complex digital designs, focusing on DDR6 technology.
What you'll do
- Lead verification strategy, execution, and signoff for complex semiconductor designs at the block and system level.
- Architect, develop, maintain, and optimize SystemVerilog and UVM testbenches and verification environments.
- Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
- Collaborate with RTL and design engineers to review specifications, identify functional gaps, and resolve complex verification failures.
- Develop scalable and reusable verification components, methodologies, and best practices.
- Provide technical guidance, mentorship, and review participation across the engineering team.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Extensive semiconductor design verification experience with technical ownership of complex verification efforts.
- Expert-level proficiency with SystemVerilog.
- Significant hands-on experience with UVM, including developing and optimizing UVM-based verification environments.
- Demonstrated experience defining verification strategies, building test plans from specifications, constrained-random testing, and coverage closure.
- Experience collaborating closely with RTL and design engineering teams throughout the verification lifecycle.
Nice to have
- Experience with DDR, memory interfaces, memory controllers, data buffers, or related semiconductor technologies.
- Experience with DDR4 and/or DDR5.
- Verification experience with complex high-speed interfaces, protocols, or mixed-signal semiconductor products.
- Experience leading verification efforts through coverage closure and signoff.
Skills: SystemVerilog, UVM, constrained-random, testbench, DDR6
More semiconductor jobs: Renesas Electronics jobs · Verification engineer jobs
First seen in our index 3 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1412 |
| Open roles in the wider Digital Design & Verification family | 96 | 3617 · 122 employers |
| Median days since first seen | 22 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, constrained-random, testbench, DDR6
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.