Principal Design Engineer, HBM - Richardson, TX, United States
Originally posted 3 June 2026 by the employer.
Lead silicon debug, design health, and system-level stability for High Bandwidth Memory (HBM) products within Micron's Heterogeneous Integration Group.
About the role
As a Principal HBM Design Engineer, you will lead cross-functional efforts to drive silicon debug, product quality, and system-level stability for high-volume High Bandwidth Memory (HBM) products. You will operate at the intersection of design, silicon, and system behavior within Micron's Heterogeneous Integration Group (HIG).
What you'll do
- Own HBM product design health through the sustaining phase, driving ECO implementation, verification, and long-term maintainability. - Define debug strategies, guide cross-functional teams, and serve as a technical authority in HBM sustaining efforts. - Lead root-cause analysis and resolution of complex silicon, system, and customer issues across multiple domains. - Drive alignment and execution across DE, PE, TD, and system teams to ensure issue resolution and product delivery. - Identify systemic issues and lead initiatives to improve yield, reliability, and performance across HBM products. - Lead critical customer escalations and system bring-up support while providing feedback into architecture, design, and verification methodologies.
What you'll need
- 8+ years of experience with a BS or 6+ years of experience with an MS in Electrical/Computer Engineering or a related field. - Deep expertise in HBM/DRAM architecture and high-speed memory interfaces. - Strong experience in silicon debug, system-level analysis, and root-cause resolution. - Proven ability to lead complex technical problems across cross-functional teams. - Strong background in digital and/or custom design and verification.
Nice to have
- Demonstrated ownership of complex silicon/system issues impacting product or customer delivery, and experience influencing architecture, design trade-offs, or product decisions. - Deep understanding of timing, margining, SI/PI, and system-level behavior and silicon correlation. - Experience with DFT, mBIST, and test-mode debug. - Proficiency in scripting languages such as Python or Perl, and experience leveraging AI-assisted tools to support design & analysis.
This role has been open 155 days — well above the 59-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
302
|
Median days open
59 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (302 roles · 59 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 302 |
| Open roles in the wider Process, Fab & Equipment family | 1486 | 10039 · 106 employers |
| Median days open | 41 d | 59 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Who's hiring in this category
- KLA Corporation · 42 open roles · median 135 d
- Micron Technology (this employer) · 40 open roles · median 41 d
- Renesas Electronics · 21 open roles · median 45 d
- Intel Corporation · 20 open roles · median 27 d
- GlobalFoundries · 14 open roles · median 67 d
- Lumilens · 13 open roles · median 78 d
How we counted: 302 open Packaging Engineering (Advanced Packaging) roles from 59 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.