Principal Architect, Performance Analysis and Modeling - Santa Clara, United States
Originally posted 11 March 2026 by the employer.
Focus on DIMC, D2D, and 3D-DRAM architectures for datacenter inference accelerators.
About the role
As a Principal Architect, Performance Analysis and Modeling on the architecture team, you will analyze emerging machine learning workloads and define hardware and software features for datacenter inference accelerators. The technical scope focuses on emerging hardware technologies such as DIMC, D2D, and 3D-DRAM alongside efficient tensor cores, storage, and collective communication techniques.
What you'll do
- Analyze emerging ML workloads, including multi-modal LLMs, CoT reasoning models, and video/audio generation, to identify functional and performance implications. - Create analytical performance models and architecture simulators to project performance across current and future generations of hardware. - Propose new hardware and software features to enable and optimize ML algorithms at the datacenter level. - Track research in ML architecture and algorithms to guide system-level design. - Collaborate across partner teams including Product, Hardware Design, Compiler, Inference Server, and Kernels.
What you'll need
- BSEE with 10+ years of industry experience, or MSEE with 8+ years of industry experience. - Background in computer architecture, hardware-software codesign, performance modeling, and ML fundamentals (particularly DNNs). - Programming fluency in C/C++ or Python. - Demonstrated experience developing analytical performance models or architecture simulators for performance analysis. - Experience tracking and evaluating machine learning algorithms and datacenter workloads.
Nice to have
- Research background with a publication record in computer architecture or machine learning venues such as ISCA, MICRO, ASPLOS, HPCA, DAC, or MLSys.
Skills: ML workloads, inference accelerators, architecture team, performance analysis, hardware software codesign
This role has been open 129 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | d-Matrix | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 473 |
| Open roles in the wider Digital Design & Verification family | 3 | 3322 · 115 employers |
| Median days open | 129 d | 77 d (+52 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: ML workloads, inference accelerators, architecture team, performance analysis, hardware software codesign
Who's hiring in this category
- Qualcomm · 79 open roles · median 86 d
- NVIDIA · 53 open roles · median 72 d
- Apple · 37 open roles · median 15 d
- AMD · 35 open roles · median 72 d
- Arm Holdings · 27 open roles · median 120 d
- Micron Technology · 21 open roles · median 99 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.