Principal Application Engineer- Timing Sign Off
Originally posted 12 August 2026 by the employer.
Support customer tapeouts diagnosing timing, power, and signoff issues in PrimeTime, PrimeShield, PrimeClosure, and PrimePower.
About the role
This role involves supporting customer tapeouts by diagnosing timing, power, and signoff issues in a customer-facing capacity.
What you'll do
- Support customer tapeouts, diagnosing timing, power, and signoff issues under real schedule pressure.
- Deploy newly developed signoff features with customers, working through beta testing, adoption blockers, and methodology integration.
- Evaluate customer requirements and translate them into actionable enhancement requests for product development.
- Build and deliver technical training content, demos, and methodology documentation.
- Replicate, debug, and escalate product issues, working across engineering, R&D, and account teams.
- Mentor applications engineers and customer design teams on timing signoff best practices.
What you'll need
- Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.
- 10+ years of hands-on experience with timing analysis and signoff tools, flows, and methodologies in a customer-facing or product development role.
- Deep working knowledge of PrimeTime, and direct experience with at least two of the following: PrimeShield, PrimeClosure, PrimePower.
- Demonstrated ability to debug complex signoff issues under tapeout pressure and propose solutions balancing accuracy, runtime, and methodology constraints.
- Strong understanding of static timing analysis fundamentals, including multi-mode multi-corner analysis, OCV, AOCV, path-based analysis, and signoff closure techniques.
- Proven ability to work effectively across global teams, including product engineering, account management, and customer design teams.
Skills: timing signoff, PrimeTime, static timing analysis, tapeout, EDA tools, methodology
This role has been open 64 days — below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
675
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (675 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 63 | 675 |
| Open roles in the wider Physical Implementation family | 106 | 1442 · 110 employers |
| Median days open | 36 d | 73 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: timing signoff, PrimeTime, static timing analysis, tapeout, EDA tools, methodology
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys (this employer) · 63 open roles · median 38 d
- Micron Technology · 44 open roles · median 46 d
- Qualcomm · 36 open roles · median 74 d
- GlobalFoundries · 33 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 71 d
How we counted: 675 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.