Principal AMS Design - Taiwan

Originally posted 14 September 2026 by the employer.

About the role

As a Principal AMS Engineer, you will architect, design, integrate, and validate high-speed analog and mixed-signal technologies across the full development lifecycle from IP definition through tapeout, bring-up, and mass production.

What you'll do

- Architect and develop analog and mixed-signal circuits and subsystems for high-speed interfaces and SoCs. - Lead architecture and integration of high-speed PHY technologies, including die-to-die, UCIe-class interfaces, DDR, HBM, and related SerDes/PHY functions. - Guide development of critical AMS functions including clocking, reference circuits, DLL/PLL-related functions, voltage monitoring, calibration, data-path circuitry, and custom analog IP. - Drive chip, package, and PCB co-design for high-speed signal integrity and power integrity. - Own AMS for PHY integration into SoCs, covering interface definition, floorplanning, clocking, timing, power intent, IO, and physical implementation considerations. - Drive designs through pre-silicon architecture and verification, tapeout, characterization, post-silicon validation, and production.

What you'll need

- Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience. - Experience in analog and mixed-signal IC design and implementation. - Background in high-speed PHY architecture and design, such as DDR, HBM, die-to-die, UCIe, SerDes, MIPI, or similar interfaces. - Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADCs/DACs, LDOs, IO, or related mixed-signal functions. - Understanding of SoC integration, including clocking, timing/STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning. - Experience with high-speed signal integrity and power integrity across chip, package, and PCB, plus silicon execution through tapeout and post-silicon validation.

Nice to have

- Direct experience with UCIe or proprietary die-to-die interfaces. - Experience with advanced packaging, chiplets, or multi-die systems. - Experience developing complete PHY subsystems from architecture through silicon validation. - Background in IO/ESD and latch-up design and qualification. - Experience with analog timing characterization and design-flow/CAD infrastructure. - Experience managing or technically leading third-party IP and design-service vendors.

Skills: AMS/PHY architecture, high-speed interfaces, clocking, SerDes, DDR, HBM