Pre‑Silicon Power Modeling Leader — x86 SoCs - TX, Austin, United States
Originally posted 16 January 2026 by the employer.
About the role
Lead SoC-level pre-silicon power modeling for embedded and client x86 programs, owning the methodology and models that translate into accurate Perf/Watt projections and robust DVFS/AVFS plans. The role establishes silicon correlation, manages program power budgets, and supports workloads across CPU, GPU, and NPU subsystems.
What you'll do
- Own the SoC power model end-to-end using converged methodology, delivering workload-based power estimates for CPU, GPU, NPU, fabric, memory, and I/O. - Define use-case power envelopes across automotive, networking, storage, industrial, and robotics segments, deriving representative workloads and KPIs. - Drive DVFS/AVFS strategy (P-states, C-states, voltage/frequency points), telemetry requirements, and early tables/guardrails for FW/BIOS enablement. - Establish IP and subsystem power budgets, running sensitivity studies to guide architectural decisions including cache sizes, fabric frequencies, and NPU/GPU configurations. - Build repeatable model-to-silicon correlation plans covering CaC, static, and dynamic splits, EDC/TDC interactions, and droop mitigation. - Lead EDA tool flows and Python-based automation pipelines using PowerArtist and PrimeTime PX to ingest FSDB/VCD activity and publish power scorecards.
What you'll need
- Demonstrated experience building top-level SoC power models with silicon correlation, including IP-level VBM integration and workload-based projections. - Hands-on expertise with EDA tools such as PowerArtist or PrimeTime PX, activity annotation (FSDB/VCD), UPF/CPF power intent, and Python automation. - Knowledge of x86 micro-architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions. - Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements, with familiarity in EDC/TDC/CaC semantics. - B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with industry experience in SoC pre-silicon power modeling.
Nice to have
- Segment experience modeling power for automotive (AEC-Q100/ASIL) use-cases, networking throughput workloads, storage I/O patterns, and industrial/robotics duty cycles. - System performance modeling familiarity with GEM5, Simics, or SystemC to align Perf/Watt predictions with architecture teams. - Experience creating PnP dashboards and regressions using Python, Jenkins, Grafana, and InfluxDB for continuous tracking.
Skills: power modeling, Perf/Watt projections, DVFS/AVFS, x86 micro-architecture, UPF/CPF, PowerArtist
This role has been open 217 days — well above the 200-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · AI ML Hardware
|
Open roles in category
29
|
Median days open
200 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (29 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 29 |
| Open roles in the wider Digital Design & Verification family | 251 | 3346 · 116 employers |
| Median days open | 198 d | 200 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: power modeling, Perf/Watt projections, DVFS/AVFS, x86 micro-architecture, UPF/CPF, PowerArtist
Who's hiring in this category
- Qualcomm · 8 open roles · median 200 d
- NVIDIA · 7 open roles · median 196 d
- SiFive · 3 open roles · median 197 d
- AMD (this employer) · 2 open roles · median 197 d
- Infineon Technologies · 2 open roles · median 194 d
- Intel Corporation · 2 open roles · median 4 d
How we counted: 29 open SoC/Chip Architecture (AI ML Hardware) roles from 11 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.