Pre-Silicon Digital Verification Engineer - Sunnyvale, United States
Originally posted 26 October 2026 by the employer.
About the role
Apple is seeking a Pre-Silicon Digital Verification Engineer for mixed signal integrated circuits. In this role, you will verify complex digital IPs for custom integrated circuits across Apple's product lines.
What you'll do
- Collaborate in developing design specifications for digital control blocks and create block and chip level verification plans. - Architect and create block level verification elements, and assist in architecting chip and system level verification environments. - Use System Verilog and UVM to develop drivers, tests, reference models, and checkers. - Own verification testbenches using formal verification, UVM based simulation, and System Verilog Assertions. - Build constrained random UVM testcases to achieve complete functional and code coverage. - Debug test failures, work with designers on fixes, and track progress toward tapeout readiness.
What you'll need
- BS degree with a minimum of 3 years of relevant industry experience. - Experience with System Verilog and UVM for developing verification components. - Experience with constrained random verification techniques and assertions. - Experience building block level verification plans and testbenches.
Nice to have
- Extensive course work in digital design and computer architecture. - Foundation in object oriented programming techniques. - Familiarity with clock domain crossing design and verification techniques. - Course work in analog circuit design.
Skills: pre-silicon, UVM, SystemVerilog, constrained random, assertions
This role has been open 0 days — well below the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 1254 |
| Open roles in the wider Digital Design & Verification family | 114 | 3345 · 116 employers |
| Median days open | 11 d | 66 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: pre-silicon, UVM, SystemVerilog, constrained random, assertions
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.