Power Feature Enablement Systems Engineer - TX, Austin, United States
Originally posted 9 September 2026 by the employer.
This role focuses on power management features and performance-per-watt attainment.
About the role
As the Power Feature Enablement Systems Engineer, you will be a cross-functional technical leader for power features workstreams on your product, guiding it from pre-silicon definition/planning through program end of life. This role focuses on the power and performance domain.
What you'll do
- Ensure seamless enablement of power management features from design through silicon validation, firmware integration, and system-level deployment.
- Lead teams to performance/watt attainment, developing strategies for test, feature enablement, debug, analysis, and defect resolution.
- Work closely with power architects to set power and performance attainment objectives and define features.
- Drive the definition, validation, enablement, and integration of power and performance management features such as C-state and P-state algorithms, IP dynamic power management, FW active power management algorithms, and thermal compensation.
- Lead cross-functional technical teams in the triage, debug, and resolution of power management feature issues.
- Provide continuous improvement feedback to cross-functional teams including the power management architecture, IP, SoC, O/S, FW, and silicon enablement team.
What you'll need
- Bachelor’s Degree (BS) in Electrical Engineering, Computer Engineering, Systems Engineering, or relevant discipline.
- Understanding of system-level power management trade-offs at hardware, firmware, and software levels.
- Understanding of system-level thermal, power, frequency, and/or voltage limited workload behavior.
- Understanding of CPU, GPU, Memory, and NPU power/performance, SW power management, and system-level trade-offs.
- Strong analytical and debugging skills, with experience in root cause analysis for power/performance issues.
- Familiarity with PC architecture, hands-on system setup, and power and performance data collection hygiene.
Nice to have
- Proven ability to deliver large cross-functional technical deliverables in a multi-site environment.
Skills: Power and Performance Attainment, System and SoC Architects, power management features, performance-per-watt, HW and SW power management, thermal management
This role has been open 35 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 470 |
| Open roles in the wider Digital Design & Verification family | 255 | 3189 · 115 employers |
| Median days open | 64 d | 79 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: Power and Performance Attainment, System and SoC Architects, power management features, performance-per-watt, HW and SW power management, thermal management
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD (this employer) · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.