Power Delivery Architect - San Jose, California, United States
Originally posted 26 June 2026 by the employer.
This role focuses on designing the power delivery system for an AI accelerator chiplet grid.
About the role
This role involves designing the complete power delivery system for AI accelerators from 48V datacenter racks to sub-1V silicon cores. The system involves a grid of hundreds of chiplets drawing thousands of amps.
What you'll do
- Architect the rack-to-silicon power delivery network, from 48V datacenter busbar power down to sub-1V silicon cores across a multi-chiplet grid.
- Own regulator integration strategy, evaluating and deploying high-frequency, multi-phase VRMs, Co-packaged Voltage Regulators (CPVR), and Vertical Power Delivery (VPD) architectures.
- Design the multi-tier decoupling capacitor hierarchy (bulk, PCB, package, and on-chip/deep trench) through simulations to maintain stable target impedance.
- Model and mitigate extreme di/dt transient events and IR drop across the 400-chiplet grid.
- Partner cross-functionally with silicon, advanced packaging (2.5D/3D interposers), and thermal teams to run full-system electro-thermal and electromagnetic co-simulations.
- Utilize AI for IR drop analysis, electromigration debugging, and power grid optimization.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Power Electronics, or a related technical field.
- 8+ years of hands-on power delivery experience spanning chip-level PDN, package-level power delivery, and system/rack-level power architecture.
- Deep knowledge of rack-to-silicon PDN design including 48V busbar architectures, VRM/CPVR/VPD technologies, multi-tier decoupling strategy, and transient current management.
- Proficiency with power delivery simulation and analysis tools, including EMIR, electrothermal, and electromagnetic co-simulation.
- Strong fundamentals in power electronics and high-current system design.
- Proven ability to drive cross-domain co-design across silicon, packaging, thermal, and system teams.
Skills: power delivery network, 48V busbar architectures, VRM/CPVR/VPD, multi-tier decoupling, electro-thermal simulation, chiplet grid
This role has been open 123 days — well above the 96-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
68
|
Median days open
96 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | persimmons | All employers we track in this specialty (68 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 68 |
| Open roles in the wider Analog & Mixed-Signal family | 1 | 1495 · 107 employers |
| Median days open | 123 d | 96 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: power delivery network, 48V busbar architectures, VRM/CPVR/VPD, multi-tier decoupling, electro-thermal simulation, chiplet grid
Who's hiring in this category
- Renesas Electronics · 13 open roles · median 104 d
- Qualcomm · 8 open roles · median 75 d
- Infineon Technologies · 7 open roles · median 69 d
- Analog Devices · 5 open roles · median 95 d
- Monolithic Power Systems · 5 open roles · median 221 d
- AMD · 4 open roles · median 86 d
How we counted: 68 open Power Electronics (Power Management) roles from 22 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.