PNR CAD SILICON DESIGN ENGINEER - Hyderabad-Design Center, India
Originally posted 5 October 2026 by the employer.
About the role
The role will involve automation of PnR flows and methodologies for 3nm & 2nm technology nodes.
What you'll do
- Develop Place and Route methodologies for various designs at advanced technology nodes.
- Work with synthesis and signoff (STA, extraction, Physical Verification) teams to achieve PPA.
- Drive power/performance/area (PPA) convergence for SOCs implementation.
- Script utilities to automate different stages of the implementation flow.
- Support design teams through multiple PnR flow stages, including chip finish flows.
What you'll need
- Master’s/Bachelor’s Degree in Electronics Engineering.
- 8-10 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm.
- Experience with industry-standard physical design tools Innovus & Fusion Compiler.
- Strong understanding of low-power flows including UPF concepts, power-gating, isolation, level-shifter, voltage areas, power-state tables, and electrical checks using FM & VSI.
- Proficiency in scripting and automation using Python, TCL with debugging capabilities.
Nice to have
- Experience in PNR flows including multi-voltage & power-gated designs.
- Experience with synthesis, STA, Physical verification domains.
- Exposure to AI/ML concepts, with strong Python proficiency.
Skills: PNR flows, Place and Route, 3nm & 2nm technology nodes, Innovus & Fusion Compiler, PPA convergence
This role has been open 0 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
631
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (631 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 631 |
| Open roles in the wider Physical Implementation family | 76 | 1430 · 108 employers |
| Median days open | 21 d | 60 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PNR flows, Place and Route, 3nm & 2nm technology nodes, Innovus & Fusion Compiler, PPA convergence
Who's hiring in this category
- Qualcomm · 122 open roles · median 38 d
- AMD (this employer) · 49 open roles · median 21 d
- Broadcom · 40 open roles · median 85 d
- NVIDIA · 37 open roles · median 60 d
- Synopsys · 29 open roles · median 48 d
- Micron Technology · 25 open roles · median 75 d
How we counted: 631 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.