PMIC Architect - San Jose, CA, United States
Own the IVR architecture end-to-end for PMIC.
About the role
As PMIC Architect, you will own the IVR architecture end-to-end for Power Management ICs, including power conversion topology, digital control engine, and analog subsystems. This role requires fluency in power electronics and mixed-signal IC design, focusing on PMIC products.
What you'll do
- Define IVR architecture, including multi-phase interleaved buck converter topology, phase count configurability, and switching frequency selection.
- Architect the digital control engine, covering per-phase duty cycle control, current balance, and transient response optimization for AI workload dynamics.
- Define requirements for analog subsystems, such as gate drivers, current sensing (DCR / integrated sense), and oscillator / clock generation.
- Oversee integrated inductor evaluation and selection, including saturation current, DCR, and Q-factor.
- Drive process node selection for Gen 1 and roadmap generations, evaluating tradeoffs in power density, analog capability, and cost.
- Translate AI compute platform power delivery requirements into product specifications and engage customers at the architecture level.
What you'll need
- 15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment.
- Deep expertise in multi-phase synchronous buck converter design, including topology selection, loop compensation, and stability analysis.
- Mixed-signal IC design fluency, covering gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes.
- Hands-on experience with integrated passive components, such as on-chip or in-package inductors and capacitors.
- Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design.
- Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization.
- Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps.
Nice to have
- Experience with kilowatt-class power delivery for AI accelerators, GPUs, or high-performance CPUs.
- Familiarity with in-package voltage regulator architectures (FIVR, LEGO-style VR, or substrate-embedded passives).
- Background in PMBus / I2C / proprietary digital power management interfaces.
Skills: PMIC architecture, buck converter, power delivery, integrated inductors, mixed-signal IC design
This role has been open 28 days — well below the 70-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
69
|
Median days open
70 d
|
Median salary
$180k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (69 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 69 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1340 · 104 employers |
| Median days open | 28 d | 70 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $180k |
Skills observed across this category: PMIC architecture, buck converter, power delivery, integrated inductors, mixed-signal IC design
Who's hiring in this category
- Renesas Electronics · 15 open roles · median 73 d
- Qualcomm · 7 open roles · median 42 d
- Analog Devices · 6 open roles · median 79 d
- Monolithic Power Systems · 6 open roles · median 182 d
- Infineon Technologies · 5 open roles · median 70 d
- AMD · 4 open roles · median 90 d
How we counted: 69 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.