Physical design Staff Application engineer
Originally posted 4 October 2026 by the employer.
Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler.
About the role
This staff application engineer role focuses on supporting customers with advanced physical design challenges on products that tape out and ship. The role involves working on advanced-node designs at 7nm, 5nm, and below using physical design tools like Fusion Compiler and ICC2.
What you'll do
- Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools, including Fusion Compiler, to achieve PPA targets.
- Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl across the RTL-to-GDS flow.
- Debug complex physical design challenges, including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints.
- Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines.
- Contribute to AI-assisted and machine learning-driven design optimization initiatives.
- Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements.
What you'll need
- Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience.
- Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, used on real tapeouts.
- Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems.
- Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigration.
- Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases.
Skills: physical design, Fusion Compiler, ICC2, TCL, Python
This role has been open 10 days — well below the 30-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
106
|
Median days open
30 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (106 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 106 |
| Median days open | 27 d | 30 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: physical design, Fusion Compiler, ICC2, TCL, Python
Who's hiring in this category
- Synopsys (this employer) · 54 open roles · median 27 d
- Cadence Design Systems · 25 open roles · median 30 d
- Keysight Technologies · 9 open roles · median 50 d
- Renesas Electronics · 9 open roles · median 63 d
- AMD · 2 open roles · median 88 d
- Arteris · 2 open roles · median 115 d
How we counted: 106 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.