Physical Design - SOC Top Lead
$200,000 - $250,000 USD yearly
Originally posted 3 August 2026 by the employer.
This role focuses on the Electron E1 processor.
About the role
What you'll do
- Floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level.
- Full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level SDC ownership.
- Full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy.
- DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles.
- Chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure.
- Bump/ball map coordination, IO ring planning, and package-aware floorplanning.
What you'll need
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience.
- 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level.
- Hands-on experience with advanced nodes.
- Experience with full-chip timing closure across multiple corners/modes on a complex SoC.
- PDN/IR-drop/EM analysis experience (Voltus or equivalent).
- Experience with chip-level DFT integration (scan stitching, MBIST, JTAG).
- Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre.
- Scripting skills in TCL, shell and python.
Nice to have
- Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map).
- Experience with non-standard/novel architectures (dataflow, tiled, NoC-based).
- Knowledge of computer architecture.
- Knowledge of physical design and ASIC implementation.
- Experience in full chip sign off convergence.
- Knowledge of circuit design, device physics, deep sub-micron technology and its implications to physical design.
- Proficiency with industry-grade physical design flow.
- Experience in integrating analog or mixed-signal macro on top-level design.
Skills: full-chip integration, timing closure, power planning, physical verification, DFT integration
This role has been open 75 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 659 |
| Open roles in the wider Physical Implementation family | 3 | 1441 · 110 employers |
| Median days open | 100 d | 60 d (+40 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: full-chip integration, timing closure, power planning, physical verification, DFT integration
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.