Physical Design Engineer- senior - Austin, Texas, United States of America, United States
$115,600 - $173,400 USD yearly
Originally posted 22 July 2026 by the employer.
About the role
As a Physical Design Engineer - Senior, you will define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance and low-power products.
What you'll do
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development. - Create architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. - Collaborate across software architecture and hardware architecture teams to develop and execute implementation strategies. - Evaluate process flow across high-level design, synthesis, place and route, timing and power use, and verification or custom circuit design/layout flow. - Utilize tools and applications, including RTL to GDS Flow and Virtuoso, to execute block/SoC or IC Package architecture and design. - Write detailed technical documentation for EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience; OR Master's degree and 1+ year of related experience; OR a PhD. - Hands-on experience with ASIC design, verification, validation, or integration. - Experience with implementation flows encompassing synthesis, place and route, and timing and power use.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. - 3 years of ASIC design, verification, validation, integration, or related work experience. - 2 years of experience with architecture and design tools. - 2 years of experience with scripting tools and programming languages. - 2 years of experience with design verification methods.
Skills: ASIC design, RTL to GDS Flow, place and route, timing and power use, Virtuoso
This role has been open 88 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 120 | 659 |
| Open roles in the wider Physical Implementation family | 162 | 1441 · 109 employers |
| Median days open | 42 d | 61 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC design, RTL to GDS Flow, place and route, timing and power use, Virtuoso
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 46 d
- AMD · 63 open roles · median 25 d
- Intel Corporation · 37 open roles · median 12 d
- Synopsys · 37 open roles · median 33 d
- NVIDIA · 36 open roles · median 71 d
- Broadcom · 30 open roles · median 98 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.