Pe Dft - India
Verification, Validation & Test
About the role
This role involves handling various aspects of DFT for high-speed mixed signal designs, including low coverage debug for Stuck-at and Transition faults, and silicon debug.
What you'll do
- Perform full DFT of Mixed Signal designs.
- Create and deploy DFT IPs.
- Debug different failures and perform low coverage analysis for Stuck-at and At-speed.
- Collaborate with cross-functional teams to develop and verify DFT structures and constraints.
- Work with Test Engineering for test program development, silicon bring-up, diagnosis, yield improvement, and silicon debug.
- Support EDA R&D teams to propose and implement new features.
What you'll need
- 8-12 years of hands-on experience in Design for Test (DFT).
- Clear understanding of key DFT concepts like Scan compression (EDT), Scan Stitching, fault models (stuck-at, delay tests, Small Delay), and OCC.
- Understanding of SOC DFT architecture and basic DFT for mixed signal designs.
- Understanding of Synthesis, RTL coding, and STA.
- Hands-on skill for scripting and flow deployment.
- Understanding of MBIST and LBIST.
- Silicon debug skills and sign-off experience.
Nice to have
- Hands-on experience with Tessent ATPG tool.
- Experience in at least one scripting language like PERL, Python, TCL, or Shell.
Market context
This role has been open 39 days — well below the 62-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
220
|
Median days open
62 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Rambus | All employers we track in this specialty (220 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 220 |
| Open roles in the wider Digital Design & Verification family | 23 | 3050 · 114 employers |
| Median days open | 39 d | 62 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 39 open roles · median 32 d
- Qualcomm · 23 open roles · median 86 d
- NXP Semiconductors · 21 open roles · median 79 d
- NVIDIA · 15 open roles · median 74 d
- Synopsys · 9 open roles · median 19 d
- Intel Corporation · 8 open roles · median 58 d
How we counted: 220 open DFT Engineering (DFT Test) roles from 50 employers tracked in the SemiconductorJobs index, counted 27 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.