Post-Silicon Validation Engineer
Astera Labs provides connectivity solutions through PCIe semiconductor-based technologies.
Originally posted 17 August 2026 by the employer.
About the role
This role involves hands-on PCIe post-silicon validation and debug, working across hardware, firmware, and software boundaries. The engineer will validate PCIe functionality across different generations, platforms, configurations, and operating conditions, focusing on PCIe link bring-up, physical-layer debug, and silicon validation.
What you'll do
- Perform hands-on PCIe post-silicon validation.
- Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
- Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
- Drive complex issues from initial failure through root-cause analysis and final resolution.
- Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
- Develop automation to improve validation coverage, debug efficiency, and regression testing.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development.
- Strong hands-on knowledge of PCIe architecture and protocol.
- Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.
- Experience working across hardware, firmware, and software boundaries.
- Scripting/programming skills, preferably Python.
- Linux knowledge and experience with Linux PCIe debug tools.
Nice to have
- Experience with PCIe Gen4/Gen5/Gen6/Gen7.
- Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
- Experience with PCIe compliance and interoperability testing.
- Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.
- Experience with PCIe switches, or networking/accelerator platforms.
- Practical experience using AI/ML tools for engineering debug and automation.
More semiconductor jobs: Astera Labs jobs · Post-silicon validation jobs · Israel jobs
First seen in our index 88 days ago, well above the 65-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
129
|
Median days since first seen
65 d
|
Category median salary (all employers)
$190k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (129 roles · 34 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 129 |
| Open roles in the wider Silicon Validation & Test family | 19 | 2480 · 122 employers |
| Median days since first seen | 56 d | 65 d (+9 d vs this employer) |
| Median salary (USD postings) | n/a | $190k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 56 d
- AMD · 17 open roles · median 51 d
- NVIDIA · 15 open roles · median 93 d
- Arm Holdings · 8 open roles · median 16 d
- Graphcore · 7 open roles · median 149 d
- Micron Technology · 6 open roles · median 221 d
How we counted: 129 open Post-Silicon Validation (Design Verification) roles from 34 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Silicon Validation & Test family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.