PCIe, CXL and Highspeed IO Validation Engineer - CA, Santa Clara, United States
Verification, Validation & Test
Originally posted 28 July 2026 by the employer.
About the role
This role involves leading and improving AMD's capabilities in highspeed IO, specifically focusing on PCI Express and Compute Express Link (CXL), multi-socket, and inter-die interfaces within the datacenter CPU post silicon validation team.
What you'll do
- Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features for High-Speed IO across all AMD Server products.
- Develop test content for focus testing and system-level stress testing of IO domain plus cross-product stress testing.
- Develop post-silicon validation infrastructure, including software, hardware, automation environment, and lab setup.
- Debug and drive root-cause analysis for SoC related issues.
- Collaborate with cross-functional teams to improve post-silicon validation test strategy, methodology, and process.
What you'll need
- Proven hands-on experience in SoC design or validation of high speed IO interfaces.
- Experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both.
- Understanding of modern x86 microprocessor architecture and Server platform architecture.
- Experience developing validation methodologies and infrastructure.
- Familiarity with programming / scripting languages (C/C++, Python, Perl, ...).
- Working knowledge of Server OSes (Linux, Windows).
- Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes.
- Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization.
- Extensive knowledge of system architecture, technical debug, and validation strategy.
- BSEE/CSE/CS with 7+ years of experience or MSEE/CSE/CS with 5+ years of experience.
Skills: PCIe, CXL, highspeed IO, post-silicon validation, debug