New College Grad - Mixed Signal Design Engineer, HBM - Richardson, TX, United States
Originally posted 2 June 2026 by the employer.
About the role
This role contributes to the development of digital and mixed-signal foundations for high-bandwidth memory (HBM) products within the Memory Systems Engineering team. You will support the integration and implementation of HBM base-die subsystems.
What you'll do
- Assist in defining and implementing digital micro-architecture for HBM base-die subsystems, including channel support logic, boot sequencing, training orchestration, configuration registers, telemetry, and reliability features. - Translate system requirements into timing, power, and area considerations while supporting interface specifications for bus protocols, clock-domain crossings, and reset strategies. - Implement and integrate synthesizable SystemVerilog RTL, covering multi-channel logic, interrupts, register maps, scan hooks, and design-for-test interfaces. - Collaborate with design verification teams to support verification planning, coverage goals, CDC/RDC checks, and debugging of RTL, testbench, and gate-level issues. - Support silicon bring-up and post-silicon validation through debug enablement and issue correlation to RTL or architecture.
What you'll need
- Bachelor’s degree or equivalent experience in Electrical Engineering or Computer Engineering. - Experience with digital build or SoC integration through academic projects, internships, or early-career industry roles. - Knowledge of SystemVerilog RTL build, clock and reset architecture, CDC/RDC methodologies, and low-power design concepts. - Understanding of design-for-debug and design-for-test principles.
Nice to have
- Exposure to post-silicon validation, silicon bring-up, or structured debug workflows. - Experience or familiarity with scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST), or related test and debug features. - Experience developing or supporting verification plans and collaborating with build verification teams to achieve coverage goals. - Interest in refining micro-architecture to improve timing and understanding build tradeoffs related to constraints and path intent.
Skills: HBM, SystemVerilog RTL design, clock-domain crossing, DFT interfaces, post-silicon validation
This role has been open 222 days — well above the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
309
|
Median days open
71 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (309 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 309 |
| Median days open | 91 d | 71 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: HBM, SystemVerilog RTL design, clock-domain crossing, DFT interfaces, post-silicon validation
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 91 d
- Synopsys · 30 open roles · median 67 d
- Qualcomm · 19 open roles · median 88 d
- Broadcom · 17 open roles · median 68 d
- SanDisk · 17 open roles · median 54 d
- NVIDIA · 7 open roles · median 34 d
How we counted: 309 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.