New College Grad - HBM Design Architect
High Bandwidth Memory (HBM) Design Architecture team developing memory solutions for AI accelerators and high-performance computing.
Originally posted 5 November 2026 by the employer.
About the role
As an HBM Design Architect on the Roadmap and Pathfinding group, you will perform first-principles architecture analysis for current and future HBM and DRAM products spanning dynamic power, PDN, thermal, timing, and area trade-offs. You will run circuit and CAD simulations to validate architectural assumptions and develop solutions for AI accelerators, high-performance computing, and data centers.
What you'll do
- Perform architecture-level analysis for HBM/DRAM products, including dynamic and static power, PDN/IR drop, thermal behavior, timing, and area trade-offs.
- Build first-principles models and contributor breakdowns (array, periphery, datapath, I/O, TSV) and correlate them with simulation and silicon data.
- Set up and run circuit simulations (SPICE/HSPICE, FineSim, PrimeSim, Spectre, or equivalent) and associated CAD flows, including schematic setup, parasitic extraction, and post-layout simulation.
- Assess the impact of new technologies on product metrics, including advanced DRAM nodes, 3D stacking, scaled-pitch hybrid bonding, and BEOL/TSV changes.
- Partner with circuit designers, process technologists, and packaging engineers to develop and quantify architectural solutions.
- Develop scripts, calculators, and automation using Python or equivalent to support modeling, simulation setup, and data analysis.
What you'll need
- BSEE or related field with 0–2 years of relevant experience, or MS/PhD with 0–2+ years.
- Solid foundation in CMOS circuit design and device physics.
- Working knowledge of DRAM fundamentals, including cell/array operation, sensing, and basic timing.
- Understanding of power delivery and power analysis (CV²f, leakage, IR drop) and thermal concepts for semiconductor dies.
- Hands-on experience with circuit simulation (SPICE/HSPICE, FineSim, or equivalent) and Cadence Virtuoso or similar CAD environments.
- Proficiency in Python, Tcl, Perl, or another scripting language.
Nice to have
- Coursework, research, or experience in DRAM/HBM design, TSV-based 3D integration, or advanced packaging.
- Exposure to PDN/power analysis tools or thermal simulation (compact thermal models, FEA/CFD).
- Familiarity with semiconductor process technology (FEOL/BEOL, interconnect materials, bonding).
- Experience using AI-enabled tools (LLMs, AI assistants, Code Assist/Roo Code, or agentic AI solutions) for engineering automation and analysis.
Skills: HBM, DRAM, SPICE, PDN, 3D stacking
More semiconductor jobs: Micron Technology jobs · SoC design jobs · Richardson jobs
This role has been open 0 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
492
|
Median days open
77 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (492 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 492 |
| Open roles in the wider Digital Design & Verification family | 105 | 3500 · 120 employers |
| Median days open | 65 d | 77 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: HBM, DRAM, SPICE, PDN, 3D stacking
Who's hiring in this category
- Qualcomm · 79 open roles · median 90 d
- NVIDIA · 63 open roles · median 78 d
- Apple · 39 open roles · median 16 d
- AMD · 37 open roles · median 71 d
- Arm Holdings · 28 open roles · median 8 d
- Micron Technology (this employer) · 20 open roles · median 89 d
How we counted: 492 open SoC/Chip Architecture (SOC Architecture) roles from 68 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.