New College Grad - Design Engineer, Circuit Design - San Jose, CA, United States
$145,000 - $246,000 USD yearly
Originally posted 23 June 2026 by the employer.
This role focuses on NAND Flash circuits and systems.
About the role
This role involves the architecture, design, simulation, and verification of NAND Flash circuits and systems. You will contribute to advanced memory solutions focusing on NAND Flash designs.
What you'll do
- Participate in multi-functional evaluations of key features and recommend architectural decisions for NAND Flash designs.
- Break down system functions into analog and/or digital circuits and design, simulate, optimize, and floor plan NAND circuitry.
- Analyze design feasibility and circuit functionality, including performance, power, and reliability.
- Validate designs through block- and chip-level simulations using industry-standard simulators and defined verification coverage.
- Collaborate with multi-functional teams to evaluate NAND die performance, power consumption, manufacturability, and root-cause analysis.
What you'll need
- Knowledge of analog design theory, loop stability analysis, device physics, and CMOS device reliability.
- Understanding of memory cell read/write operations, array architecture, and unit-block verification methodologies.
- Experience in transistor-level analog and digital IC design using CMOS, including simulation and post-layout analysis.
- Experience designing analog/digital blocks such as bandgap references, regulators, charge pumps, ADC/DACs, oscillators, comparators, sensors, or custom logic.
- Working knowledge of digital design flow (Verilog, RTL synthesis, logic simulation, place and route), scripting languages (Perl, Python, or C++), and Verilog-A basics.
- Experience working in AI Enabled environments or willingness to leverage AI tools to support engineering productivity, automation, and data-driven workflows.
Nice to have
- Exposure to AI Assisted or Applying AI techniques, such as Python scripting or data-driven automation, to improve design or verification efficiency.
- Proficient knowledge of memory cell test flow and hands-on lab experience with IC characterization and debugging.
- Familiarity with circuit-level reliability fundamentals, including aging effects and device stress mechanisms.
- Advanced expertise with analog and digital simulators such as HSPICE, Verilog, XA, or Finesim.
- Experience with Cadence design environments and LVS/DRC tools, along with deeper expertise in scripting or digital implementation flows.
Skills: NAND circuits, memory cell, bandgap, regulator, charge-pumps, ADC
This role has been open 164 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND circuits, memory cell, bandgap, regulator, charge-pumps, ADC
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.