NAND Custom Test Circuit Design Engineer
$148,000 - $252,000 USD yearly
Originally posted 12 November 2026 by the employer.
About the role
As a NAND Custom Test Circuit Design Engineer at Micron Technology, you will develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs across global design and verification teams.
What you'll do
- Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
- Drive Design for Test (DFT) requirements for custom NAND test circuits, including controllability and observability, test-mode architecture, fault coverage, built-in self-test, and ATPG or pattern-generation interfaces.
- Validate custom test circuits using XA simulations, Verilog simulations, and mixed-signal validation environments.
- Apply Design for Manufacturing (DFM) principles to improve process-window margin and yield through PVT and Monte Carlo analysis, mismatch assessment, and silicon-data-driven optimization.
- Collaborate with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects.
- Support Product Engineering during first-silicon bring-up, debug, characterization, failure isolation, and simulation-to-silicon correlation.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field with 2+ years of experience.
- Hands-on experience in custom/analog circuit design, mixed-signal design, memory peripheral circuit design, or Product Engineering with transistor-level circuit and silicon-debug exposure.
- Strong understanding of CMOS device operation, transistor-level circuit design, leakage mechanisms, parasitics, PVT sensitivity, timing, loading, noise margin, power, and reliability principles.
- Proficiency in XA or equivalent fast transistor-level simulation, Verilog, and mixed-signal validation methodologies.
- Solid understanding of DFT and DFM methodologies, including fault models, coverage metrics, scan, built-in self-test, test-point insertion, ATPG awareness, and Monte Carlo analysis.
- Proficiency in Python and scripting for simulation automation, regression analysis, result extraction, and waveform processing.
More semiconductor jobs: Micron Technology jobs · Test engineer jobs · San Jose jobs
First seen in our index 0 days ago, well below the 41-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
661
|
Median days since first seen
41 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (661 roles · 85 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 661 |
| Open roles in the wider Silicon Validation & Test family | 176 | 2438 · 121 employers |
| Median days since first seen | 58 d | 41 d (−17 d vs this employer) |
| Median salary (USD postings) | n/a | $176k |
Who's hiring in this category
- Teradyne · 86 open roles · median 41 d
- Infineon Technologies · 48 open roles · median 35 d
- Renesas Electronics · 48 open roles · median 35 d
- Texas Instruments · 34 open roles · median 48 d
- Qualcomm · 30 open roles · median 55 d
- Micron Technology (this employer) · 26 open roles · median 59 d
How we counted: 661 open Silicon Test Engineering (DFT Test) roles from 85 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Silicon Validation & Test family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.