NAND Array Engineer - San Jose, United States
Solidigm
San Jose, United States
Full-time
7 days ago
Digital Design & SoC Architecture
Originally posted 28 September 2026 by the employer.
This role drives characterization of array erase, program, and read operations for 3D NAND technology.
About the role
What you'll do
- Design, plan, and execute NAND memory cell and array characterization experiments.
- Develop and optimize trims to improve Read Window Budget (RWB) and Raw Bit Error Rate (RBER).
- Apply NAND device physics principles to explain experimental data and trim parameters.
- Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams.
- Interface with wafer fabrication teams to drive Sort and Wafer-Level Reliability (WLR) Design of Experiments (DOEs).
- Conduct comprehensive data analysis to identify and communicate trade-offs.
- Build predictive models for NAND behavior based on empirically observed data.
- Develop and maintain scorecards to track NAND device degradation.
- Release optimized trims to the production flow.
- Drive improvements in back-end test yields through trim optimization and advanced screening techniques.
What you'll need
- Master's or PhD in Electrical Engineering, Microelectronics, or a closely related field.
- 3+ years of industry experience in semiconductor memory technologies and products.
- Deep understanding of NAND cell and array operations, including array reliability physical mechanisms and characterization techniques.
- Strong foundation in semiconductor device physics and process flows.
- Proficiency in statistical analysis methodologies and tools.
- Hands-on programming experience in C, C++, Python, and/or JMP.
Nice to have
- Experience with 3D NAND architecture and advanced memory scaling challenges.
- Familiarity with wafer fab processes and Sort/WLR test methodologies.
- Track record of releasing trims or process improvements to high-volume manufacturing.
- Experience with machine learning or advanced modeling techniques for semiconductor data.
Market context
This role has been open 6 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Solidigm | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 27 d | 69 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.