MTS - DPG Layout - Hyderabad - Phoenix Aquila, India
Originally posted 14 August 2026 by the employer.
About the role
This role involves the design and development of full chip layout within Micron Technology's DRAM Engineering Group in India.
What you'll do
- Drive the design and development of full chip layout, spanning analog, digital, memory, ESD, and full chip EM/IR aspects.
- Establish layout guidelines for successful execution of full chip layouts.
- Perform layout verification (LVS/DRC/Antenna) and quality checks.
- Deliver full chip and block-level layouts on time with acceptable quality.
- Collaborate with Design, Verification, CAD, DTCO, and PI teams to define and execute layout solutions.
- Guide junior team members in sub-block level layouts and review their work.
What you'll need
- 15+ years experience in analog/custom layout design in advanced CMOS process.
- Expertise in Cadence VLE/VXL and Calibre DRC/LVS.
- Hands-on experience in Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier.
- Hands-on experience handling various memories like DRAM, SRAM, CAM, OTP.
- Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices).
- Experience in scripting and automation.
Skills: full chip layout, analog layout design, Cadence VLE/VXL, Calibre DRC/LVS, DRAM, SRAM, CAM, OTP
This role has been open 51 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: full chip layout, analog layout design, Cadence VLE/VXL, Calibre DRC/LVS, DRAM, SRAM, CAM, OTP
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.