Modelling Lead (SystemC / Virtual-Platform Architect) - San Jose, United States
Originally posted 24 June 2026 by the employer.
Architect a SystemC/TLM-2.0 virtual platform that firmware runs on pre-RTL.
About the role
This role involves building an executable model of the chip before silicon exists, settling decisions on datapath latency, throughput, buffer sizing, and control-loop tuning. The reference models will become golden checkers for the verification team, and the platform will run real firmware months ahead of RTL.
What you'll do
- Own a SystemC/TLM-2.0 virtual platform including MCU (ISS-backed), peripherals, memory map, UCIe transactor, and host stub.
- Develop architecture/performance models for architectural trade studies, end-to-end datapath throughput and latency, FIFO/buffer sizing, and design-space/configuration exploration.
- Create golden reference models for DV scoreboards.
- Develop behavioral models of analog and control circuits.
- Partner with the FE architect and firmware lead to ensure coherence between model, RTL, and firmware views.
What you'll need
- 8+ years in architecture/performance modelling or virtual-platform development for complex SoCs.
- Strong SystemC and TLM-2.0; solid modern C++.
- Experience building or leading a virtual platform / ESL model that real firmware ran on for pre-silicon bring-up.
- Experience integrating a third-party ISS (e.g., Arm or RISC-V) into a SystemC/TLM platform, modelling buses, memory maps, and peripherals.
- Architecture/performance modelling judgment, including knowing what to abstract versus model faithfully.
- Comfort spanning hardware micro-architecture and embedded software.
Nice to have
- Familiarity with High-speed serial links and die-to-die / chiplet interconnects, and link-layer concepts such as FEC and equalization (e.g. PCIe, UALink, Ethernet or memory-semantic interconnects like CXL).
- Experience feeding golden models into a UVM/DV verification flow.
- Modelling for mixed-signal or optical/SerDes systems, including control-loop / plant modelling.
- High-throughput datapath modelling.
Skills: SystemC/TLM-2.0, virtual platform, architecture models, performance modelling, UCIe transactor
This role has been open 73 days — below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
79 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 472 |
| Open roles in the wider Digital Design & Verification family | 8 | 3201 · 115 employers |
| Median days open | 73 d | 79 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: SystemC/TLM-2.0, virtual platform, architecture models, performance modelling, UCIe transactor
Who's hiring in this category
- Qualcomm · 73 open roles · median 88 d
- NVIDIA · 56 open roles · median 71 d
- Apple · 36 open roles · median 12 d
- AMD · 34 open roles · median 60 d
- Arm Holdings · 27 open roles · median 115 d
- Micron Technology · 22 open roles · median 107 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.