$145,600 - $218,400 USD yearly
Support post-silicon bring-up and validation of mixed signal IPs such as DDRPHY and SerDes.
Originally posted 5 November 2026 by the employer.
About the role
The Mixed Signal SVE team is seeking an engineer to support silicon bring-up and validation of mixed signal IPs such as DDRPHY and SerDes. You will collaborate with PHY Design, Firmware, PTE, and Software teams to bring up PHYs and debug complex issues.
What you'll do
- Lead bring-up, debugging, and optimization of DDR/SerDes PHYs across post-silicon teams.
- Proactively identify and resolve issues to ensure successful product launches.
- Provide post-release support for PHY-related customer issues.
- Develop firmware and execute regression testing.
- Generate clear and detailed test reports and documentation.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 4+ years of ASIC design, verification, validation, integration, or related work experience (or Master's degree and 3+ years, or PhD and 2+ years).
Nice to have
- Hands-on experience with DDR/SerDes test development, debugging, and characterization.
- Proficiency in firmware development and scripting, with Python preferred.
- Solid understanding of JEDEC and other electrical/protocol specifications.
- Strong grasp of PHY circuitry fundamentals including DLLs, I/O, and calibration.
- Familiarity with signal integrity and probing techniques for memory buses.
- Skilled in using lab instruments including oscilloscopes, spectrum analyzers, and logic analyzers.
- Experience with hands-on lab work, including soldering and system instrumentation.
- Experience applying machine learning or data science techniques to hardware validation or silicon debug.
- Knowledge of statistical modeling and data visualization for large-scale silicon test datasets.
- Ability to build and maintain automated pipelines for data collection, labeling, and model training.
- Understanding how AI can be used to enhance lab instrumentation workflows and regression analysis.
Skills: silicon bring-up, DDRPHY, SerDes, post-silicon, JEDEC
More semiconductor jobs: Qualcomm jobs · Silicon validation jobs · San Diego jobs
First seen in our index 7 days ago, well below the 42-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
476
|
Median days since first seen
42 d
|
Category median salary (all employers)
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (476 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 476 |
| Open roles in the wider Silicon Validation & Test family | 158 | 2467 · 122 employers |
| Median days since first seen | 41 d | 42 d (+1 d vs this employer) |
| Median salary (USD postings) | n/a | $167k |
Skills observed across this category: silicon bring-up, DDRPHY, SerDes, post-silicon, JEDEC
Who's hiring in this category
- AMD · 66 open roles · median 39 d
- Qualcomm (this employer) · 46 open roles · median 41 d
- Apple · 29 open roles · median 21 d
- Micron Technology · 29 open roles · median 49 d
- NVIDIA · 27 open roles · median 43 d
- Microchip Technology · 21 open roles · median 90 d
How we counted: 476 open Post-Silicon Validation (Silicon Validation) roles from 68 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Silicon Validation & Test family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.