Microarchitect / RTL Design - Memory Subsystem - Palo Alto, United States

Originally posted 12 August 2026 by the employer.

This role owns the AI-driven microarchitecture and RTL design of the memory subsystem going into production silicon.

About the role

This role involves owning the AI-driven microarchitecture and RTL design of the memory subsystem going into production silicon, focusing on memory controllers, memory hierarchy management, and memory-side accelerators.

What you'll do

• Own the memory subsystem RTL end-to-end, including DDR/HBM controller design through code generation, lint, CDC, synthesis, and timing closure.
• Design and implement memory controllers, including DDR5/LPDDR5X PHY-side controller logic, HBM3/HBM3E pseudo-channel controllers, command scheduling, refresh management, and ECC/RAS engines.
• Architect the memory hierarchy, including multi-level cache controllers, scratchpad memory managers, coherency protocol engines, prefetch engines, and bandwidth partitioning/QoS mechanisms.
• Design memory-side accelerators such as near-memory compute logic, scatter-gather DMA engines, address translation/remapping units, compression/decompression engines, and intelligent prefetchers.
• Define and maintain interface specifications, including DDR PHY, HBM PHY, on-chip SRAM, AXI/ACE/CHI for memory-facing fabric ports, and custom interfaces for near-memory accelerator datapaths.
• Support verification bring-up with memory timing models, protocol-compliant BFMs, SVA assertions for JEDEC protocol compliance, coverage plans, and architectural documentation for closure.

What you'll need

• 5+ years in RTL design with at least one advanced-node tapeout experience involving memory subsystems (DDR/LPDDR/HBM controllers, cache hierarchies, or memory-intensive SoC subsystems).
• Deep familiarity with JEDEC memory standards: DDR5/LPDDR5X command/address protocols, timing parameters, training sequences, and/or HBM2E/HBM3 pseudo-channel architecture, stack addressing, and interleaving schemes.
• Hands-on experience designing or owning memory controller blocks including command schedulers, bank state machines, refresh engines, read/write turnaround optimization, and PHY interface timing (DFI or proprietary).
• Experience with multi-level cache design (tag/data arrays, replacement policies, coherence protocols), scratchpad controllers, or unified memory architectures with partitioning and QoS.
• Clear, synthesizable, lint-clean SystemVerilog RTL with strong design habits: parameterization for multi-standard support (DDR5/HBM3), modularity for channel/pseudo-channel instantiation, and configurability for different capacity/bandwidth targets.
• Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI, ACE, CHI), and power management for memory subsystems.
• Strong Python skills for design automation, performance modeling, regression infrastructure, and tooling.

Nice to have

• Experience with HBM integration: interposer-level considerations, PHY calibration, thermal management impacts on refresh.
• Familiarity with CXL memory pooling, Type 3 device controllers, or disaggregated memory architectures.
• Near-memory or processing-in-memory (PIM) design experience.
• Low-power design techniques: DVFS-aware memory scheduling, partial-array self-refresh, clock gating of idle channels, power gating of unused banks.
• FPGA prototyping experience (Xilinx Vivado/Vitis) with DDR MIG or HBM subsystem IP integration.
• SVA assertions for JEDEC protocol compliance (command sequencing, timing parameter checking, training state machines).
• Performance modeling: experience building or using cycle-accurate memory system simulators (e.g., DRAMSim, Ramulator) to validate microarchitectural decisions.
• Domain-specific research contributions: publications or patents in memory systems, memory scheduling algorithms, or memory-centric compute architectures for ML workloads.

Skills: memory subsystem RTL, DDR/HBM controller, memory hierarchy, ML accelerator datapaths, JEDEC memory standards