Microarchitect / RTL Design - Interconnect & Fabric - Palo Alto, United States

Originally posted 12 August 2026 by the employer.

Architect microarchitecture and RTL design of the on-chip interconnect fabric.

About the role

As a Member of the Technical Staff, you will own the AI-driven microarchitecture and RTL design of the on-chip interconnect fabric and high-speed I/O data movement subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for NoC routers, crossbar switches, high-speed fabric bridges, and peer-to-peer data transfer engines.

What you'll do

• Own on-chip fabric RTL end-to-end from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure.
• Design and implement AMBA-based interconnect fabrics, including AXI/ACE/CHI-compliant crossbar switches, network interfaces, and protocol converters.
• Architect NoC routers and topologies, including virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, and QoS-aware arbitration.
• Design high-speed I/O fabric bridges and peer-to-peer engines, including PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic, and peer-to-peer DMA controllers.
• Work with principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into architecture.
• Build and maintain RTL infrastructure for an in-house AI-driven flow: design automation scripts, NoC configuration generators, regression flows, and integration collateral.

What you'll need

• Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
• AMBA Protocol Expertise: Deep familiarity with ARM AMBA protocol suite—AXI4/AXI5, ACE/ACE-Lite, CHI, and legacy AHB/APB.
• NoC/Fabric Design: Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes, virtual channel management, flow control, and QoS mechanisms.
• High-Speed I/O Integration: Experience with HSIO bridge logic—PCIe root complex/endpoint bridge design, CXL.io/CXL.mem/CXL.cache protocol translation, or custom chip-to-chip links (UCIe, proprietary die-to-die).
• SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits.
• Python: Strong skills for design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure, and tooling.

Nice to have

• Experience with coherent multi-chip/multi-die interconnect architectures (chiplet-based designs, UCIe, BoW).
• Familiarity with hardware coherence protocols: MOESI/MESIF state machines, snoop filter design, directory-based coherence.
• Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis.
• Low-power design techniques for interconnect: clock gating idle ports, power gating unused links, link-level power states (L0s/L1), dynamic frequency/width scaling.
• FPGA prototyping experience (Xilinx Vivado/Vitis), especially with AXI interconnect IPs, NoC IPs (Versal), or custom fabric implementations.
• SVA assertions for protocol compliance: AXI ordering rules, CHI transaction flows, deadlock detection, and livelock/starvation monitors.
• Prior IP building and delivery experience for NoC IPs, AXI interconnect IPs, PCIe controllers, or CXL endpoint/switch IPs.
• Performance modeling: experience building or using NoC simulators (e.g., BookSim, Garnet) or system-level traffic models to validate fabric microarchitecture.
• Domain-specific research contributions: publications or patents in on-chip networks, interconnect architectures, or high-performance data movement for ML/HPC workloads.

Skills: on-chip fabric RTL, AMBA-based interconnect, NoC routers, high-speed I/O fabric bridges, coherent multi-chip