[Japan] Accelerator IP Design Engineer (ASIC, RTL) - Kawasaki, Kanagawa
Design and optimize the Dynamic Neural Accelerator AI processor IP targeting energy-efficient edge inference.
About the role
Edgecortix is seeking an Accelerator IP Design Engineer to deliver RTL/logic and ASIC designs for deep-learning edge inference processors. The role focuses on RTL design and module-level verification for the Dynamic Neural Accelerator AI processor IP.
What you'll do
- Execute RTL design and module-level verification for Edgecortix inference accelerator IP modules. - Participate in logic synthesis, static timing analysis (STA), and power estimation workflows. - Propose and implement low-level micro-architectural optimizations for area, power, and placeability/routability under concrete process and budget constraints. - Collaborate with architects and compiler engineers to evaluate architectural specs and determine implementation methods for new functionality. - Perform SoC system integration using third-party IPs and assist with IP- and system-level verification and debugging using SystemVerilog and UVM. - Maintain engineering standards across code reviews, technical documentation, testing processes, continuous integration, and release engineering.
What you'll need
- Proven ability to write clean, readable, synthesizable RTL. - Familiarity with AXI, Avalon, or similar bus protocols. - Experience in low-power RTL design and timing optimization. - Experience performing logic synthesis using Cadence or Synopsys tools, including writing timing constraints and power intent definitions. - Experience with power analysis tools such as Joules or PowerPro. - Understanding of physical design issues and fixed-point arithmetic for approximating floating-point computations. - Experience with verification using SystemVerilog and UVM. - Scripting and automation skills using TCL, Python, and Make, plus basic programming knowledge in statically typed languages such as C++ or Java.
Nice to have
- Experience with DDR, PCI-E, MIPI CSI, or other high-speed protocols.
This role has been open 124 days — well above the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
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See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1081 |
| Open roles in the wider Digital Design & Verification family | 8 | 3359 · 116 employers |
| Median days open | 124 d | 66 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.