Memory PHY - Technical Lead - TX, Austin, United States
Originally posted 16 September 2026 by the employer.
Lead the integration and post-silicon support for third-party Memory/Serdes PHY and high-speed mixed-signal IP across AMD SoCs.
About the role
As part of the high-speed physical interface (PHY) and mixed-signal IP team, you will serve as the technical owner for the integration and support of third-party Memory/Serdes PHY and mixed-signal IP across AMD products. The scope spans architecture, SoC integration, post-silicon validation, and production.
What you'll do
- Serve as the technical owner for third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs throughout the entire lifecycle. - Collaborate directly with third-party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs. - Partner with SoC integration teams to ensure the electrical, logical, and physical quality of IP integration. - Support package and PCB design teams with signal integrity and power integrity analysis, debug, and optimization. - Partner with post-silicon validation teams in directing first-silicon bring-up, debug, characterization, compliance testing, and ATE production test support. - Drive system-level architectural decisions balancing performance, power, area, cost, and implementation constraints.
What you'll need
- Experience designing high-speed mixed-signal IP and integrating IP into an SoC. - Design knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks (e.g., CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO). - Experience with FinFET semiconductor technologies at and below 7nm. - Basic understanding of RTL, logic design, and digital circuits. - Understanding of transistor-level design, system architecture, and SoC integration.
Nice to have
- Experience with interface protocols such as HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, or MIPI. - Python and/or Perl programming experience in a UNIX environment. - Laboratory experience, including hands-on use of test equipment such as BERT, oscilloscope, and logic analyzer. - B.S. or M.S. in Electrical Engineering.
Skills: Memory/Serdes PHY, high-speed mixed-signal IP, HBM, LPDDR, DDR, PCIe, Ethernet, signal integrity
This role has been open 35 days — well below the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
234
|
Median days open
72 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (234 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 234 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1428 · 107 employers |
| Median days open | 40 d | 72 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Memory/Serdes PHY, high-speed mixed-signal IP, HBM, LPDDR, DDR, PCIe
Who's hiring in this category
- Synopsys · 31 open roles · median 36 d
- AMD (this employer) · 26 open roles · median 40 d
- Qualcomm · 20 open roles · median 63 d
- Cadence Design Systems · 19 open roles · median 155 d
- Micron Technology · 15 open roles · median 36 d
- Apple · 12 open roles · median 22 d
How we counted: 234 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 46 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.