Memory Layout Design Engineer - IND-Bangalore Electronic City - S1, India
Originally posted 3 August 2026 by the employer.
About the role
This role is for a Memory Layout Design Engineer with a focus on advanced submicron FinFET processes.
What you'll do
- Apply layout guidelines, new process rules, and technical requirements for high-quality layouts.
- Manage scheduling, timelines, and layout floor-planning.
- Ensure end-to-end deliverables are completed with high quality and within the planned schedule.
- Adapt to new methodologies and communicate with SOC and library teams.
- Lead teams, train junior engineers, and document layout methodologies and guidelines.
- Lead new technology reviews to document layout methodologies, flows, and guidelines.
What you'll need
- 8+ years of experience with a Bachelor's degree or 6+ years with a Master's degree.
- Proficiency in Cadence Virtuoso Layout, Layout XL, Cadence Schematic Capture.
- Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.
- Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
- Extensive experience with physical verification tools such as Calibre and Hercules (DRC, LVS, ERC, Antenna, and Softcheck Errors).
- Proficiency in floor-planning, hierarchy layout, and chip integration.
- Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
Nice to have
- Experience with memory compilers.
- Knowledge of AI, layout automation, and script/SKILL programming.
Skills: memory layout, Cadence Virtuoso, FinFET, physical verification, DRC LVS
This role has been open 62 days — below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 287 |
| Median days open | 51 d | 69 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: memory layout, Cadence Virtuoso, FinFET, physical verification, DRC LVS
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom (this employer) · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.