Member of Technical Staff - Microarchitect / RTL Design - Palo Alto, United States
Originally posted 16 April 2026 by the employer.
About the role
As a Member of the Technical Staff on the RTL Design team, you will own the microarchitecture and RTL design of SoC blocks and subsystems targeted for production silicon. You will define and revise block-level microarchitecture specifications for hardware accelerator blocks.
What you'll do
- Own the RTL design flow at the frontend, incorporating feedback from lint, clock domain crossing (CDC), synthesis, and timing closure stages. - Work directly with the principal architect to refine microarchitectural specifications and resolve area, timing, and power trade-offs. - Define and maintain interface specifications (including AXI, AXI-Stream, or custom protocols) for block-level and subsystem-level integration. - Build and maintain RTL design infrastructure, including automation scripts, regression flows, and lint/CDC waivers. - Collaborate with design verification teams by supporting bring-up with reference models, assertions, test plans, and architectural documentation. - Support FPGA prototyping on Xilinx platforms for functional validation.
What you'll need
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. - 5+ years of experience in RTL design with at least one advanced-node tapeout on specialized hardware accelerators. - Expertise in synthesizable SystemVerilog with parameterization, modularity, and lint-clean coding practices. - Hands-on block-level experience with compute datapaths or data movement, including MAC arrays, vector units, SRAM controllers, or DMA engines. - Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, and AMBA protocols (AXI, AHB, APB). - Python proficiency for design automation, regression infrastructure, and tooling.
Nice to have
- Low-power design experience including clock gating, power gating, multi-voltage domains, and UPF. - FPGA prototyping experience with Xilinx Vivado/Vitis. - Familiarity with SIMD/VLIW execution pipelines or instruction-driven datapath design. - Experience writing SystemVerilog Assertions (SVA) and functional coverage for design-side verification. - Prior IP building and delivery experience with DMA controllers, memory subsystems, or on-chip interconnects.
This role has been open 130 days — well above the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1081 |
| Open roles in the wider Digital Design & Verification family | 6 | 3359 · 116 employers |
| Median days open | 103 d | 66 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.