Manager, Digital Design - San Jose, California, United States
Digital Design & SoC Architecture
$216,000 - $240,000 USD yearly
Originally posted 17 September 2026 by the employer — open 0 days.
About the role
This role involves leading the front-end digital design of high-performance PCIe, CXL, UAL, and Ethernet devices for rack-scale AI infrastructure.
What you'll do
- Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
- Drive delivery of complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
- Partner with architecture and system teams to translate PCIe, CXL, UAL, and Ethernet requirements into robust, scalable digital implementations.
- Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.
- Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
- Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
- Lead, mentor, and develop a team of 6–8 digital design engineers.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with PCIe, CXL, UAL, and Ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
- Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices.
- Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
- Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.
Nice to have
- Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
- Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
- Building design blocks with large physical floorplan sizes.
- Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
Market context
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
921
|
Median days open
62 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (921 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 921 |
| Open roles in the wider Digital Design & Verification family | 52 | 3004 · 115 employers |
| Median days open | 38 d | 62 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Who's hiring in this category
- Qualcomm · 134 open roles · median 58 d
- AMD · 60 open roles · median 67 d
- Synopsys · 56 open roles · median 31 d
- NXP Semiconductors · 53 open roles · median 64 d
- NVIDIA · 49 open roles · median 50 d
- Analog Devices · 38 open roles · median 75 d
How we counted: 921 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
San Jose, California, United States
On-site
$216,000 - $240,000 USD yearly
18 days ago