Manager, ATE Test Engineering - San Jose, California, United States
$195,000 - $250,000 USD yearly
Originally posted 28 August 2026 by the employer.
Manage ATE Test Engineering for CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor technologies.
About the role
This role involves leading the ATE Test engineering organization in San Jose, CA, driving high-speed, high-performance products from silicon bring-up through high-volume manufacturing.
What you'll do
- Build, mentor, and lead a team of ATE Test engineers for connectivity products in AI infrastructure.
- Define end-to-end ATE test strategies and plans for high-speed connectivity products.
- Guide tester platform selection and develop load boards, interface hardware, and test solutions.
- Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.
- Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.
- Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods.
What you'll need
- Bachelor's degree in electrical engineering or related technical field.
- 8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.
- 3+ years of managerial experience building and leading a Test engineering team.
- Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
- Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.
- Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations.
Nice to have
- Master’s or PhD in Electrical Engineering or related field.
- Experience leading wafer-sort and final-test hardware development, including high-speed load-board design.
- Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG.
- Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.
- Proficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platforms.
This role has been open 30 days — slightly above the 25-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
472
|
Median days open
25 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (472 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 472 |
| Open roles in the wider Silicon Validation & Test family | 19 | 2149 · 110 employers |
| Median days open | 29 d | 25 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 50 open roles · median 10 d
- Infineon Technologies · 37 open roles · median 32 d
- Renesas Electronics · 33 open roles · median 28 d
- AMD · 26 open roles · median 26 d
- Micron Technology · 25 open roles · median 28 d
- Qualcomm · 25 open roles · median 13 d
How we counted: 472 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.