Logic Design Engineer - CA, Santa Clara, United States
Digital Design & SoC Architecture
Originally posted 24 July 2026 by the employer.
Join our mixed-signal high-speed IO team.
About the role
This role is for a Logic Design Engineer to join a mixed-signal high-speed IO team, focusing on delivering high-quality, industry technologies to the market.
What you'll do
- Analyze complex digital design problems and propose architecture/micro-architecture solutions
- Develop Verilog RTL and Functional Behavioral Models
- Drive/develop ASIC design flows and scripts
- Create microarchitecture specifications
- Work with the Design Verification team to ensure functional correctness
- Support silicon bring-up and diagnostics
What you'll need
- Experience in high-speed interfaces such as DDR, GDDR, HBM, and high-speed SERDES
- Experience in designs with multiple power domains
- Experience in designs with multiple clock domains
- Experience in behavior modeling for Analog Circuits
- BS/ MS in electrical engineering or equivalent
Nice to have
- Proven experience in analog mixed-signal design from specification to successful silicon
- Experience in industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, power estimation, etc.
Skills: Verilog RTL, micro-architecture, high-speed interfaces, multiple power domains, ASIC CAD tools