Originally posted 18 September 2026 by the employer — open 1 day.
This role focuses on Data Center GPU products.
About the role
This role involves driving IP domain and power-management validation for AMD Data Center GPU products across pre-silicon, bring-up, post-silicon enablement, and system-level debug. The role specifically focuses on SMU hardware validation and power-management features like bootcode, clocking, fuse, SMN, SMUIO, thermal, RSMU, and security-related interactions.
What you'll do
- Own SMU hardware validation planning and execution across emulation, ASIC bring-up, post-silicon enablement, regression, and sustaining phases.
- Develop validation plans for SMU sub-blocks and power-management features, including bootcode, clocking, fuse, SMN, SMUIO, thermal, RSMU, security-related interactions, and system-management functions.
- Lead debug triage, root-cause analysis, and issue closure across hardware, firmware, platform, diagnostics, and system-level interactions.
- Build and improve automation, validation content, debug-analysis scripts, and regression checks.
- Review RTL, specifications, firmware interfaces, register maps, and validation collateral.
- Support lab-based and system-level debug using platform tools, firmware logs, register-level analysis, and standard measurement equipment.
What you'll need
- Strong experience in SoC domain validation, hardware features, firmware interactions, subsystem communication, and system-level debug.
- Independent validation planning, issue triage, root-cause analysis, and closure.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Strong experience in semiconductor validation, silicon bring-up, SoC validation, firmware validation, or hardware/software integration.
- Hands-on experience with power-management validation, SMU/PMFW functionality, SoC control fabrics, clocking, reset, fuse, thermal, voltage-regulator, or platform-management features.
- Experience developing validation plans, test content, automation, and debug methodologies for complex SoC or GPU products.
- Strong debug skills across hardware, firmware, software, diagnostics, and platform interactions.
- Experience with emulation, simulation, or FPGA/prototyping environments.
- Proficiency in Python and C/C++ for automation, test infrastructure, or debug-analysis tools.
- Familiarity with Linux, lab bring-up, register-level debug, firmware logs, and platform debug tools.
- Ability to execute independently, manage priorities, influence cross-functional teams, and drive technical issues to closure.
Skills: SoC domain validation, power-management validation, silicon bring-up, debug triage, Data Center GPU
This role has been open 1 day — well below the 52-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
314
|
Median days open
52 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (314 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 314 |
| Open roles in the wider Silicon Validation & Test family | 135 | 2024 · 111 employers |
| Median days open | 45 d | 52 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: SoC domain validation, power-management validation, silicon bring-up, debug triage, Data Center GPU
Who's hiring in this category
- AMD (this employer) · 49 open roles · median 45 d
- Micron Technology · 26 open roles · median 23 d
- Qualcomm · 25 open roles · median 80 d
- Graphcore · 19 open roles · median 95 d
- Microchip Technology · 18 open roles · median 48 d
- NVIDIA · 18 open roles · median 17 d
How we counted: 314 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.