Lead SoC Architect - CA, San Jose, United States
$234,780 - $402,480 USD yearly
Originally posted 26 June 2026 by the employer. Relisted by the employer on 23 October 2026.
About the role
Lead the architecture definition and technical direction of SoCs deployed across AI, Data Center, Security, Communications, and Embedded Computing applications. This role defines overall architecture across heterogeneous compute, advanced memory systems, interconnects, and hardware acceleration engines.
What you'll do
- Own and lead the architecture of SoCs, spanning multi-processor subsystems, coherent and non-coherent interconnects, memory and cache hierarchies, advanced I/O, and AI, networking, storage, compute, and crypto acceleration. - Define long-term SoC architectural strategy aligned with product, roadmap, and customer requirements. - Develop SoC architecture specifications covering compute, memory, accelerators, on-chip and off-chip interconnect, RAS, security, boot/configuration, and SoC management subsystems. - Guide cross-functional execution across RTL design, verification, physical design, firmware, software, and platform teams. - Evaluate processor IP, including x86, ARM, and RISC-V cores, compute accelerators, and PCIe, CXL, Ethernet, DDR, UCIe, and UAL protocols. - Create flexible and modular subsystem architectures deployed across chiplet, monolithic, or 3D form factors while leading PPA trade-off decisions.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or a related field. - Extensive technical experience in heterogeneous SoC architecture and high-bandwidth interconnect design. - Demonstrated experience balancing performance, power, area, and cost (PPA) trade-offs across complex silicon programs. - Deep technical experience evaluating or integrating high-speed protocols including PCIe, UCIe, UAL, or Ethernet. - Experience delivering clear architecture specifications and supporting pre-silicon design/verification through post-silicon validation.
Nice to have
- Proven track record defining and delivering architecture for complex heterogeneous SoCs in advanced nodes. - Expertise in x86, ARM, or RISC-V based processor subsystems and heterogeneous acceleration. - Technical knowledge of PCIe, CXL, Ethernet, DDR, UCIe, and UAL protocol specifications and features. - Technical background across interconnect fabrics, memory and I/O subsystems, multi-chiplet partitioning, and chiplet interconnect standards. - Proficiency with architectural modeling and performance simulation frameworks. - Patents, publications, or major architectural wins in SoC architecture.
Skills: SoC architecture, heterogeneous compute, AI acceleration, memory hierarchy, performance modeling
This role has been open 119 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 473 |
| Open roles in the wider Digital Design & Verification family | 255 | 3322 · 115 employers |
| Median days open | 73 d | 77 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: SoC architecture, heterogeneous compute, AI acceleration, memory hierarchy, performance modeling
Who's hiring in this category
- Qualcomm · 79 open roles · median 86 d
- NVIDIA · 53 open roles · median 72 d
- Apple · 37 open roles · median 15 d
- AMD (this employer) · 35 open roles · median 72 d
- Arm Holdings · 27 open roles · median 120 d
- Micron Technology · 21 open roles · median 99 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.