Lead RTL Design Engineer

Originally posted 30 April 2026 by the employer.

About the role

The Lead RTL Design Engineer will own microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP integration. You will work from architecture specification through synthesis-ready RTL, collaborating with architecture, verification, physical design, and firmware teams to tape out a power-efficient SoC.

What you'll do

- Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, interfaces, and PPA targets. - Define and drive on-chip networks, interconnects, and data movement across the fabric in collaboration with physical design. - Define memory subsystem interfaces, including data movement, ordering, synchronization behavior, and scratchpad/TCM structures. - Lead the architecture of configuration, scheduling, and execution models on the fabric, including multi-kernel support and HW/SW co-design with compiler teams. - Drive power architecture across clocking, reset, power domains, and low-power strategies using UPF-driven flows. - Author uArch specification documents, mentor engineering teammates, review RTL, and support silicon bring-up and lab debug.

What you'll need

- 8+ years of RTL design experience with tape-out ownership of dataflow-based designs, on-chip networks, memory subsystems, or peripheral integration on a processor or accelerator SoC. - Deep proficiency in SystemVerilog for synthesis-clean, lint-clean, and timing-aware RTL implementation of state machines, arbiters, and datapath logic. - Solid understanding of parallel execution models such as dataflow, SIMD, or systolic array architectures, including token-based synchronization. - Hands-on experience with on-chip memory design (SRAM wrappers, scratchpad/TCM, banking, memory-mapped register interfaces) and memory compiler toolchains. - Practical experience with low-power RTL techniques including UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic. - Familiarity with standard on-chip bus protocols (AXI, AHB, APB, TileLink, or NoC equivalent) and experience with SDC constraints, STA reports, and synthesis QoR.

Nice to have

- Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management. - Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations. - Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases. - Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and tape-out credits on edge-AI, IoT, or wearable SoCs at 12nm or below. - Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation. - Exposure to AI framework graph formats (ONNX, TFLite) or experience with formal verification of flow-control logic, deadlock freedom, and bus protocol compliance.