Lead Product Engineer - San Jose, United States
$119,000 - $221,000 USD yearly
Originally posted 21 October 2026 by the employer.
About the role
This role focuses on high-performance and power-critical CPU and GPU implementation and methodology. You will handle full-chip and block-level implementation from RTL to Signoff.
What you'll do
- Execute full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization. - Drive timing closure methodologies for setup, hold, power, and area optimization. - Implement low-power design techniques using UPF/CPF, power gating, multi-voltage domains, clock gating, and leakage optimization. - Develop scripts, utilities, and methodologies to automate workflows and improve productivity and design quality. - Collaborate with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams. - Debug and analyze complex design issues across floorplanning, clock tree synthesis, routing, signal integrity, IR drop, and electromigration.
What you'll need
- Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration. - Experience with timing closure methodologies for setup, hold, power, and area optimization. - Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization. - Automation skills with experience developing scripts and utilities to improve productivity and design quality. - Familiarity with industry-standard implementation and signoff tools.
Nice to have
- Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages. - Exposure to machine learning and AI-assisted optimization techniques. - Understanding of advanced technology nodes (5nm and below) and challenges including congestion, variability, power integrity, and manufacturability. - Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity. - Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation.
Skills: RTL to Signoff, Place and Route, Timing Closure, CTS, Floorplanning, UPF/CPF
This role has been open 0 days — well below the 180-day median for Physical Design roles.
Physical Design · Digital Backend
|
Open roles in category
39
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Median days open
180 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (39 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 39 |
| Open roles in the wider Physical Implementation family | 180 | 1464 · 110 employers |
| Median days open | 0 d | 180 d (−180 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: RTL to Signoff, Place and Route, Timing Closure, CTS, Floorplanning, UPF/CPF
Who's hiring in this category
- Micron Technology · 4 open roles · median 120 d
- Qualcomm · 4 open roles · median 99 d
- Intel Corporation · 3 open roles · median 12 d
- SiTime · 3 open roles · median 89 d
- Altera · 2 open roles · median 216 d
- Analog Devices · 2 open roles · median 202 d
How we counted: 39 open Physical Design (Digital Backend) roles from 22 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.