Lead Logic Design for UALink IP/Subsystem Engineer - Bengaluru, Karnataka, India
Originally posted 10 September 2026 by the employer — open 0 days.
This role focuses on UALink-based IP/subsystems for high-bandwidth, low-latency data movement.
About the role
This role leads RTL and microarchitecture development for UALink-based IP/subsystems.
What you'll do
- Lead UALink IP/subsystem RTL development.
- Translate protocol requirements into detailed microarchitecture.
- Design high-performance control and data-path logic.
- Work on buffering, arbitration, flow control, ordering, and error handling.
- Develop and review SystemVerilog RTL.
- Drive performance, area, power, and latency optimization.
- Collaborate with verification, SoC integration, and physical design teams.
- Debug complex functional and integration issues.
- Support silicon debug and issue resolution.
What you'll need
- 6–10 years of RTL and microarchitecture experience.
- Experience with high-speed interconnects.
- Strong understanding of data movement, flow control, arbitration, and buffering.
- Excellent SystemVerilog/Verilog skills.
- Experience with CDC, lint, synthesis, and timing.
- Strong debugging and technical leadership skills.
Nice to have
- Direct UALink experience.
- Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
- Experience with AI/accelerator or high-performance compute SoCs.
Skills: RTL development, microarchitecture, SystemVerilog, high-speed interconnects, UALink
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
935
|
Median days open
63 d
|
Median salary
$180k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (935 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 935 |
| Open roles in the wider Digital Design & Verification family | 40 | 3042 · 114 employers |
| Median days open | 73 d | 63 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $180k |
Skills observed across this category: RTL development, microarchitecture, SystemVerilog, high-speed interconnects, UALink
Who's hiring in this category
- Qualcomm · 130 open roles · median 53 d
- AMD · 55 open roles · median 63 d
- NXP Semiconductors · 52 open roles · median 59 d
- NVIDIA · 51 open roles · median 47 d
- Synopsys · 42 open roles · median 77 d
- Marvell Technology · 40 open roles · median 117 d
How we counted: 935 open Digital/RTL Design (RTL Design) roles from 99 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.