Lead Full chip EM/IR analysis Engineer - Hyderabad-Sattva, India
Originally posted 28 September 2026 by the employer.
About the role
This role focuses on building, executing, and signing off on Power and EMIR closure for IP/Full chip SOC.
What you'll do
- Drive Power and EMIR closure for design blocks and full-chip integration.
- Align EMIR analysis phases with Physical Design (PD) milestones.
- Analyze EMIR violations and propose implementation choices.
- Define EMIR signoff strategy, including IR drop and electromigration analysis.
- Coordinate bump allocation and power rail alignment with integration teams.
- Maintain and improve EMIR flow.
What you'll need
- Expertise in Synthesis, ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
- Expertise in Signoff tools like Redhawk_Sc, Voltas for EMIR, PT-PX for Power signoff, and Primetime for Timing.
- Strong scripting experience in Shell, Python, Perl, TCL, UNIX.
- Familiarity with DFx and scan architecture for EMIR considerations.
- Ability to analyze current profile and engage with SIPI team for probe pad/interposer runs.
- Bachelors or Masters degree in Electrical Engineering.
Nice to have
- Minimum 7 to 10 years of relevant work experience.
- Worked as a technical lead for at least a few full chip projects.
- Must be using AI technologies in day to day problem solving.
Skills: EM/IR analysis, Power closure, electromigration, Redhawk_Sc, Voltas
This role has been open 1 day — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
627
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (627 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 43 | 627 |
| Open roles in the wider Physical Implementation family | 70 | 1420 · 109 employers |
| Median days open | 28 d | 64 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: EM/IR analysis, Power closure, electromigration, Redhawk_Sc, Voltas
Who's hiring in this category
- Qualcomm · 114 open roles · median 40 d
- AMD (this employer) · 44 open roles · median 28 d
- Broadcom · 40 open roles · median 78 d
- NVIDIA · 38 open roles · median 53 d
- Synopsys · 27 open roles · median 56 d
- NXP Semiconductors · 25 open roles · median 77 d
How we counted: 627 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.