Lead Formal Verification Engineer - TX, Austin, United States
Originally posted 8 May 2026 by the employer. Relisted by the employer on 9 October 2026.
About the role
AMD is seeking a Lead Formal Verification Engineer to define and drive formal verification strategy, methodology, and adoption across graphics and GPU IP. The role partners with architecture, design, and verification teams to expand formal verification across the hardware development lifecycle.
What you'll do
- Define and drive formal verification strategy, methodology, and technical roadmap for graphics IP. - Lead formal verification efforts for complex GPU and processor designs while improving coverage, quality, and scalability. - Develop and deploy advanced verification techniques to solve convergence and verification problems. - Drive development of reusable infrastructure, automation, and workflows to improve verification productivity. - Partner with architecture, design, and verification teams to influence design quality and verification planning. - Research and evaluate emerging formal verification applications in areas such as security, safety, low power, and architectural verification.
What you'll need
- Undergrad degree required. - In-depth knowledge of formal verification methodologies, algorithms, proof engines, and practical applications across complex digital designs. - Proven expertise in SystemVerilog Assertions (SVA), property development, and abstract model creation. - Experience solving formal convergence problems through techniques such as induction, abstraction, reduction, and decomposition.
Nice to have
- Master or PhD degree in Computer Science, Computer Engineering, or Electrical Engineering. - Expert-level experience with formal verification tools such as JasperGold, VC Formal, Murphi, theorem provers, or similar EDA solutions. - Demonstrated success delivering verification for large-scale processor architectures, including GPU, CPU, AI accelerator, or high-performance compute designs, with understanding of computer architecture and graphics pipelines. - Proven experience developing formal verification infrastructure supporting functional property verification, datapath verification, equivalence checking, or security verification.
Skills: formal verification, functional verification, UVM, simulation, verification methodology, graphics IP design
This role has been open 178 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 92 | 1254 |
| Open roles in the wider Digital Design & Verification family | 251 | 3346 · 116 employers |
| Median days open | 56 d | 66 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal verification, functional verification, UVM, simulation, verification methodology, graphics IP design
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD (this employer) · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.