Lead Emulation Engineer - Bengaluru, Karnataka, India
Originally posted 27 August 2026 by the employer.
Work with CXL, Ethernet, NVLink, PCIe, and UALink semiconductor technologies.
About the role
This role involves leading the deployment and execution of complex SoC/IP verification on hardware emulation platforms. You will contribute to Astera Labs' Intelligent Connectivity Platform, which integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor technologies.
What you'll do
- Lead emulation strategy and execution for complex SoC/IP designs.
- Develop and maintain emulation environments for large-scale ASIC/SoC designs.
- Bring up RTL designs on emulation platforms and debug compilation, mapping, and runtime issues.
- Develop and execute emulation-based verification plans.
- Enable software and firmware teams to execute workloads on emulated hardware.
- Optimize emulation builds for performance, capacity, and compile/runtime efficiency.
What you'll need
- 6-10 years of experience.
- Strong experience with ASIC/SoC emulation.
- Hands-on experience with platforms such as Cadence Palladium, Synopsys ZeBu, or equivalent.
- Strong understanding of RTL and digital design.
- Experience with SystemVerilog/Verilog.
Skills: hardware emulation, Cadence Palladium, Synopsys ZeBu, RTL, SystemVerilog/Verilog, UVM
This role has been open 31 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1157
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1157 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1157 |
| Open roles in the wider Digital Design & Verification family | 54 | 3077 · 114 employers |
| Median days open | 65 d | 63 d (+2 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: hardware emulation, Cadence Palladium, Synopsys ZeBu, RTL, SystemVerilog/Verilog, UVM
Who's hiring in this category
- AMD · 101 open roles · median 38 d
- Qualcomm · 97 open roles · median 52 d
- NVIDIA · 85 open roles · median 70 d
- Synopsys · 65 open roles · median 23 d
- SiFive · 56 open roles · median 55 d
- NXP Semiconductors · 51 open roles · median 81 d
How we counted: 1157 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.