Lead Digital Verification Engineer
$200,000 - $230,000 USD yearly
Originally posted 18 February 2026 by the employer.
About the role
Drive functional verification of complex SoC/IP designs from specification through tapeout, owning verification strategy and methodology standards. The role guides verification execution for the company's product lines based on its Fabric architecture.
What you'll do
- Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones. - Author and review verification plans mapping specifications to features, stimulus strategies, coverage goals, and sign-off criteria. - Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors. - Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases. - Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across simulation runs. - Lead full-chip verification covering boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions. - Manage regression frameworks, coordinate simulation-to-emulation handoff, and support running gate-level simulations for sign-off.
What you'll need
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field. - 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution. - Deep expertise in UVM-based testbench architecture and constrained-random verification methodology. - Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages. - Demonstrated track record of driving functional and code coverage closure to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs. - Strong understanding of SoC building blocks including processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, and peripherals. - Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
Skills: functional verification, UVM-based testbench, constrained-random stimulus, functional coverage, ASIC/SoC design verification
This role has been open 129 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1241 |
| Open roles in the wider Digital Design & Verification family | 7 | 3322 · 115 employers |
| Median days open | 31 d | 65 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: functional verification, UVM-based testbench, constrained-random stimulus, functional coverage, ASIC/SoC design verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.