Lead Architect, Custom Silicon - USA - Texas - Richardson, United States
$131,900 - $241,500 USD yearly
Originally posted 3 November 2025 by the employer.
About the role
The Lead Architect, Custom Silicon is responsible for defining and driving the architecture of custom silicon solutions, including complex ASICs and SoCs. This role requires cross-disciplinary collaboration with design, verification, hardware, firmware, and software teams to deliver custom silicon products from concept through tape-out.
What you'll do
- Define and own the architecture and technical specifications for custom silicon products from concept through tape-out. - Lead requirement gathering, trade-off analysis, partitioning, and high-level design, optimizing for performance, power, area, scalability, and cost. - Guide the design and integration of major IP blocks, processing subsystems, memory and I/O, high-speed interfaces, and custom accelerators. - Oversee architectural execution to ensure design aligns with specifications, and develop strategies for architecture validation, bring-up, and post-silicon debug. - Ensure security, safety, and system-level design compliance adhering to standards such as ISO 26262 and IEC 61508. - Investigate, evaluate, and integrate third-party IP, presenting technical concepts and progress to internal teams, management, and external partners.
What you'll need
- Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field. - Deep experience architecting custom silicon, ASIC, or SoC designs across digital or mixed-signal domains. - Expertise in hardware system partitioning, IP integration, interconnect protocols, memory hierarchies, and clock/power domain management. - Strong knowledge of top-down architecture flows, performance modeling, EDA tools, and verification strategies. - Thorough understanding of modern interface standards, including AXI, PCIe, DDR/LpDDR, MIPI, and USB. - Familiarity with multi-discipline integration, including analog, RF, and software/firmware/hardware interfaces.
Nice to have
- Master’s Degree in Electrical Engineering, Computer Engineering, or a related field. - 15 years of experience in custom silicon, ASIC, or SoC development with a track record of leading architecture. - Demonstrated project leadership in multi-site or cross-disciplinary environments. - Experience in domains such as Physical AI, automotive, networking, storage, security, or advanced compute. - Involvement in strategic planning, IP/vendor evaluations, and cross-functional technical reviews. - History of patents, publications, or industry engagement.
Skills: architecture, custom silicon, ASICs, SoCs, performance, power, area
This role has been open 222 days — well above the 201-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · AI ML Hardware
|
Open roles in category
30
|
Median days open
201 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (30 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 30 |
| Open roles in the wider Digital Design & Verification family | 48 | 3346 · 116 employers |
| Median days open | 222 d | 201 d (+21 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: architecture, custom silicon, ASICs, SoCs, performance, power
Who's hiring in this category
- Qualcomm · 8 open roles · median 201 d
- NVIDIA · 7 open roles · median 197 d
- Intel Corporation · 3 open roles · median 5 d
- SiFive · 3 open roles · median 198 d
- AMD · 2 open roles · median 198 d
- Infineon Technologies · 2 open roles · median 195 d
How we counted: 30 open SoC/Chip Architecture (AI ML Hardware) roles from 11 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.