Layout Designer - San Jose, CA, United States
$95,680 - $220,480 USD yearly
Originally posted 22 June 2026 by the employer.
About the role
As a Layout Designer, you will develop and prepare multi-dimensional layouts, provide detailed drawings of semiconductor devices from schematics and related geometry, verify data integrity, and lead major block developments. You will collaborate across global teams including TD, design, verification, and CAD.
What you'll do
- Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices from schematics. - Plan, coordinate, and deliver major blocks and product revisions while maintaining data integrity and quality control. - Coordinate logistics and resource allocations across globally distributed design and layout environments to meet project deadlines. - Improve layout efficiency through the development of automation and new methodologies. - Interface and communicate across functional groups including TD, design, verification, and CAD.
What you'll need
- AS in Electronics, Electrical Engineering, or a related field plus 5+ years of direct experience in semiconductor layout design. - Deep solid understanding of EDA tools, including Cadence Virtuoso, Synopsys, and Calibre. - Experience developing and applying custom layout, floor-planning, signal-planning, and power-planning methodologies. - In-depth understanding of design rules and strong physical verification analysis and debugging skills. - Ability to debug problems through root-cause analysis and find effective solutions. - Understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient work processes.
Skills: semiconductor layout design, Cadence Virtuoso, DRC/LVS, floor-planning, signal-planning
This role has been open 123 days — well above the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 673 |
| Open roles in the wider Physical Implementation family | 79 | 1489 · 110 employers |
| Median days open | 92 d | 63 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: semiconductor layout design, Cadence Virtuoso, DRC/LVS, floor-planning, signal-planning
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.